Data Converters for Wireless Standards

Data Converters for Wireless Standards




Wireless communication is witnessing tremendous growth with proliferation of different standards covering wide, local and personal area networks (WAN, LAN and PAN). The trends call for designs that allow 1) smooth migration to future generations of wireless standards with higher data rates for multimedia applications, 2) convergence of wireless services allowing access to different standards from the same wireless device, 3) inter-continental roaming. This requires designs that work across multiple wireless standards, can easily be reused, achieve maximum hardware share at a minimum power consumption levels particularly for mobile battery-operated devices.
All this calls for higher levels of system integration of both the radio and the digital baseband parts. It also calls for radio design solutions with mixed signal strategies that take full advantage of technology scaledown by moving functions, such as channel select filtering, modulation and demodulation, to the digital domain. Central to achieving these goals is the design of data converters for these emerging standards in the context of technology and market trends.
Data Converters for Wireless Standards presents the design of such converters and introduces the underlying circuit design principles. As such the book will serve as a reference for IC and mixed signal designers, design managers and project leaders in industry, particularly those in the wireless semiconductor industry. The book could also serve as a reference or a text for a first year graduate course on the subject for electrical and/or computer engineering majors.



Published by
Published 01 January 1983
Reads 3
EAN13 0306480069
License: All rights reserved
Language English

Legal information: rental price per page €. This information is given for information only in accordance with current legislation.

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List of Figures List of Tables Preface 1.INTRODUCTION 1Background 2Motivation and Goals 3Organization 2.OVERVIEW OF WIRELESS RECEIVER ARCHITECTURES 1Introduction 2Receiver Architecture 2.1Superheterodyne Architecture 2.2ZeroIF Architecture 2.3LowIF Architecture 2.4Wideband IF Double Conversion Architecture 3Multistandard Receiver Architecture 4Summary 3.LOW POWER ADC DESIGN 1Introduction 2ADCCharacterizations of 3ADC ArchitecturesReview of 3.1Flash ADC 3.2Interpolating and Folding ADC 3.3TwoStep ADC 3.4Oversampling ADC
ix xiii xv 1 1 4 5
7 7 7 8 9 10 10 12 13 15 15 15 17 17 17 19 19
3.5Pipeline ADC 4Overview of Pipeline ADC Designs 4.1Key Building Blocks 4.1.1SwitchedCapacitor DAC and Residue Amplifier 4.1.2SubADC 4.1.3SampleandHold 4.2Digital Error Correction 4.3Design Considerations 4.3.1CapacitorsSize of 4.3.2Capacitor Matching 4.3.3Amplifier Architecture 4.3.4Amplifier Requirements 4.3.5Error Tolerances 5Power Optimization Techniques 5.1Optimizing the Stage Resolution 5.2Dynamic Comparator 5.3Capacitor/Amplifier Scaling 5.4Dynamic Biasing 6Summary PROTOTYPE DESIGN: ADC FOR WLAN(DSSS)/WCDMA 1Introduction 2Applications 3Architecture 4HighSpeed OTA 4.1OTA Requirements 4.2OTA Topology 4.2.1DC Gain 4.2.2GainBandwidth 4.2.3Slew Rate 4.2.4Thermal Noise 4.3CMFB 4.4Results 5Comparator 6Clock Generator 7SmartBiasing Technique 8Prototype Implementation
20 21 21 22 22 23 23 26 26 27 28 28 31 32 32 33 34 34 37
39 39 39 40 42 42 43 44 44 44 45 45 45 46 47 49 49
9Performance of the Prototype ADC 10Summary DESIGN CONSIDERATIONS OF LOW VOLTAGE ADCS 1Introduction 2Challenges in Low Voltage ADC Design 2.1Low Voltage CMOS Switches 3Devices 4Clock Boosting 5SwitchedOpamp 6A Modified Switchedopamp Technique 6.1Input Stage 6.2High Speed Design Techniques 7Summary ADC FOR BLUETOOTH/WLAN(FHSS)/HOMERF 1Applications 2System Level Design 3A Switchedopamp MDAC 4Opamp Design 4.1DC Gain 4.2Frequency Response 4.3Slew Rate 4.4Noise 4.5CommonMode Feedback (CMFB) 5Comparator Design 6Clock Generator 7Digital Correction Circuit 8Performance 9Summary HIGHRESOLUTION DAC DESIGN TECHNIQUES 1Review of DAC Architectures 1.1Current Steering DAC 1.2SwitchedCapacitor DAC 1.3Resistor String DAC 2Intrinsic Matching of ResistorString DAC 2.1Resistor Matching Model
49 50 53 53 54 56 58 59 60 62 62 66 68 71 71 73 74 75 76 77 78 79 80 81 83 84 84 86 91 91 91 93 94 94 95
2.2Design Techniques for Improved Resistor Matching 2.2.1Reducing Random Errors 2.2.2Reducing Gradient Errors 3Summary CONTROL DAC FOR 3G (UMTS) TRANSCEIVERS 1Applications 2Design Specifications 3Architecture 4Design of Resistor Strings 5ClassAB Output Buffer 6Deglitching Circuit 7Performance of the Prototype DAC 8Summary CONCLUSION
97 97 99 101 103 103 104 104 107 108 110 112 114