Low Power Networks-on-Chip

Low Power Networks-on-Chip


287 Pages


In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.



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Published 24 September 2010
Reads 1
EAN13 9781441969118
Language English

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Low Power Networks-on-Chip