The Design of Low Noise Oscillators

The Design of Low Noise Oscillators

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English

Description

The tremendous growth in wireless and mobile communications has placed stringent requirements on channel spacing and, by implication, on the phase noise of oscillators. Compounding the challenge has been a recent drive toward implementations of transceivers in CMOS, whose inferior l/f noise performance has usually been thought to disqualify it from use in all but the lowest-performance oscillators.
Low noise oscillators are also highly desired in the digital world. The continued drive toward higher clock frequencies translates into a demand for ever-decreasing jitter.
There is a need for a deep understanding of the fundamental mechanisms governing the process by which device, substrate, and supply noise turn into jitter and phase noise. Existing models generally offer only qualitative insights, however, and it has not always been clear why they are not quantitatively correct.
The Design of Low Noise Oscillators offers a new time-variant phase noise model. By discarding the implicit assumption of time- invariance underlying many other approaches, this model is capable of making quantitative predictions of the phase noise and jitter of different types of oscillators. It is able to attribute a definite amount of phase noise to every noise source in the circuit. Because of its time-variant nature, the model also takes into account the effect of cyclostationary noise sources in a natural way. It details the precise mechanism by which low frequency noise, such as l/f noise, upconverts into close-in phase noise. An important new understanding is that rise and fall time symmetry controls such upconversion. More important, it suggests practical methods for suppressing this upconversion, so that good oscillators can be built in technologies with notoriously poor l/f noise performance (such as CMOS or GaAs MESFET).
The Design of Low Noise Oscillators will be of interest to both analog and digital circuit as well as RF circuit designers.

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Published by
Published 01 January 1983
Reads 6
EAN13 0306481995
License: All rights reserved
Language English

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1Introduction 1.1Organization
Contents
2Frequency Instability Fundamentals 2.1 Introduction to Frequency Instability 2.1.1Frequency Domain 2.1.2Time Domain 2.2Frequency Instability Characterization 2.2.1Phase Noise 2.2.2Timing Jitter
3
Review of Existing Models 3.1TunedTank Oscillators 3.2Ring Oscillators
1 2
5 5 6 8 9 10 13
17 17 24
vii
TimeVariant Phase Noise Model
4
4.5
5
Jitter and Phase Noise in Ring Oscillators
79
31
5.2
79 80 84 86 87 90 92 93 96 96 98 99 99 100 110
5.1
4.3
4.6 4.7 4.8
4.1 4.2
Impulse Response Model for Excess Phase Response to Sinusoidal Input 4.2.1Perturbation CurrenttoPhase Transformation 4.2.2PhasetoVoltage Transformation 4.2.3Simulation and Experimental Verification Phase Noise and Jitter due to Random Noise 4.3.1Phase Noise 4.3.2Phase Jitter Upconversion of Low Frequency Noise 4.4.1Calculation of Cornerthe Noise 4.4.2Simulation and Experimental Verification Other TimeVariant Effects 4.5.1Cyclostationary Noise Sources 4.5.2Voltage Dependent Capacitors Amplitude Response Relationship to Previous Models Summary
viii
5.5 5.6
4.4
THE DESIGN OF LOW NOISE OSCILLATORS
5.3 5.4
The Impulse Sensitivity Function for Ring Oscillators 5.1.1Equal Rise and Fall Times 5.1.2Unequal Rising and Falling Times Expressions for Jitter and Phase Noise in Ring Oscillators 5.2.1SingleEnded CMOS Ring Oscillators 5.2.2Differential CMOS Ring Oscillators 5.2.3Bipolar Differential Ring Oscillator CorrelatedNoise Sources Design Implications in Ring Oscillators 5.4.1Differential vs. SingleEnded 5.4.2Optimum Number of Stages 5.4.3Lowering the Effect of Correlated Noise Sources 5.4.4The Effect of Tail Current Noise Source Experimental Results Summary
31 41 41 44 45 48 49 54 55 55 61 65 65 69 71 75 77
CONTENTS
6Phase Noise in Differential LC Oscillators 6.1Tank Amplitude 6.2Noise Sources 6.2.1Stationary Noise Sources 6.2.2Cyclostationary Behavior in the Presence of a Tail Capacitor 6.3Tail Current Noise Source 6.4Experimental Results and Design Implications 6.5Summary
111 111 114 116 117 119 121 128
7the Model to Multiple Noise SourcesExtension of 129 7.1Phase Response129 7.2Phase Noise due to Multiple Stochastic Noise Processes137 7.3Summary142
8
A
B
C
Conclusion
Relationship between Jitter and Phase Noise
Power Spectral Density of the Output
The ISF of an Ideal LC Oscillator
DCalculation of the ISF D.1Direct Impulse Response Calculation D.2Calculation of the Impulse Response from the SteadyState Solution
EPhase Noise and Jitter in PhaseLocked Loops E.1A Brief Review of PLLs E.1.1 First Order Loop
143
145
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157 157 158
161 161 161
ix
THE DESIGN OF LOW NOISE OSCILLATORS
F
x
E.2
E.1.2Higher Order Loops E.1.3Frequency Multiplication Phase Noise and Jitter in PLLs E.2.1VCO Noise E.2.2Other Sources of Noise E.2.3Phase Noise and Jitter in First Order Loops E.2.4Jitter and Phase Noise in Higher Order Loops E.2.5The Effect of the Frequency Divider
Describing Function Analysis of Oscillators
Bibliography
163 167 169 169 170 170 175 177
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