Oversampled Delta-Sigma Modulators

Oversampled Delta-Sigma Modulators

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English

Description

The analysis of the quantization noise in delta-sigma modulators is not a trivial task. State-of-the-art analysis methods include modelling the quantization noise as a uniform distributed white noise. However, it is not uncommon to observe limit cycle oscillations and tones at the output of a delta-sigma modulator. In most of the applications, these limit cycles and tones are strictly objectionable. Such an application, for instance, is a Fractional-N PLL frequency synthesizer, where idle tones and limit cycles generated from the delta-sigma modulator directly appear in the synthesized RF waveform as spurious components. The relatively small conversion bandwidth is another important limitation of delta-sigma modulators. Due to their oversampling nature, delta-sigma modulators have been used in low frequency applications.
Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies presents theorems and their mathematical proofs for the exact analysis of the quantization noise in delta-sigma modulators. Extensive mathematical equations are included throughout the book to analyze both single-stage and multi-stage architectures. It has been proved that appropriately set initial conditions generate tone free output, provided that the modulator order is at least three. These results are applied to the design of a Fractional-N PLL frequency synthesizer to produce spurious free RF waveforms. Furthermore, the book also presents time-interleaved topologies to increase the conversion bandwidth of delta-sigma modulators. The topologies have been generalized for any interleaving number and modulator order.
Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies is full of design and analysis techniques. The book contains sufficient detail that enables readers with little background in the subject to easily follow the material in it.
Oversampled Delta-Sigma Modulators: Analysis, Applications, and Novel Topologies will be of interest to graduate students, researchers, and practising circuit designers in the areas of delta-sigma based data converters and Fractional-N PLL frequency synthesizer design.

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Published 21 January 2013
Reads 3
EAN13 0306487284
License: All rights reserved
Language English

Legal information: rental price per page €. This information is given for information only in accordance with current legislation.

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Contents
Preface
1.
2.
3.
INTRODUCTION 1.1AIMS ANDMOTIVATIONS 1.2ORIGINAL CONTRIBUTIONS 1.3OUTLINE OF THERESEARCHMONOGRAPH
BASIC PRINCIPLES OF DELTASIGMA MODULATION 2.1NYQUISTRATECONVERTERS 2.2QUANTIZATIONNOISE 2.3OVERSAMPLINGADVANTAGE 2.4MODULATION 2.5LIMITCYCLEOSCILLATIONS ANDTONES 2.5.1Dithering 2.5.2Chaotic Modulators 2.6HIGHERORDER MODULATORS 2.6.1Singlestage Architectures 2.6.2Multistage Architectures 2.7MULTIBIT CONVERTERS 2.8STATEOFTHEARTANALYSIS
xi
1 1 4 5
7 8 10 13 15 21 21 23 23 24 25 27 28
ANALYSIS OF MASH DELTASIGMA MODULATORS WITH DC INPUTS31 3.1INTRODUCTION32
viii
4.
5.
OVERSAMPLED DELTASIGMA MODULATORS
3.2NONLINEARDIFFERENCEEQUATIONS 3.2.1Firstorder Modulator 3.2.2Higherorder MASH Modulator 3.3STATISTICS OF THEQUANTIZERERRORSEQUENCE 3.3.1Preliminaries 3.3.2Firstorder Modulator 3.3.3Higherorder MASH Modulator 3.4SIMULATIONRESULTS 3.5OUTPUTSPECTRUM 3.6DIGITALREALIZATION OFIRRATIONALINITIALCONDITION 3.7CONCLUSION
35 35 40 43 43 45 52 62 70 71 74
ANALYSIS OF SINGLESTAGE DELTASIGMA MODULATORS WITH DC INPUTS79 4.1MOTIVATIONBEHIND THEWORK79 4.2UNIFORMQUANTIZER IN THENOOVERLOADREGION80 4.3NONLINEARDIFFERENCEEQUATIONS83 4.3.1Secondorder Modulator83 4.3.2Higherorder Modulator86 4.4NOOVERLOADSTABILITYCRITERION95 4.5SOLUTION TO THE NONLINEAR DIFFERENCEEQUATION99 4.6STATISTICS OF THEQUANTIZER ERRORSEQUENCE106 4.6.1Secondorder Modulator107 4.6.2Higherorder Modulator108 4.7FUNDAMENTALRESULT109 4.8SIMULATIONRESULTS109 4.9OUTPUT SPECTRUM112 4.10ERRORFEEDBACKTOPOLOGY116 4.11CONCLUSION118
FRACTIONALN PLL FREQUENCY SYNTHESIZERS119 5.1INTRODUCTION120 5.2ANALYSIS OFPLLS121 5.2.1Smallsignal Model122 5.2.2Secondorder Systems124 5.2.3Chargepump PLL128 5.3THEFRACTIONALN CONCEPT131 5.3.1First Generation FractionalN PLL Synthesizers132 5.3.2for Modulus ControlHigherorder Modulation 134 5.4DESIGN ANDSIMULATION OFFRACTIONALN PLL FREQUENCY SYNTHESIZERS138 5.4.1Linear Model of the ChargePump PLL138 5.4.2Design Issues141
OVERSAMPLED DELTASIGMA MODULATORS
6.
5.4.3Computer Simulation Model 5.4.4Overall FractionalN PLL Simulation Results 5.5PIPELINEDIMPLEMENTATION OFMASH MODULATORS 5.6CONCLUSION
145 152 157 165
ix
TIMEINTERLEAVED DELTASIGMA MODULATORS167 6.1INTRODUCTION168 6.2BLOCK DIGITAL FILTERING APPROACH170 6.3TIMEINTERLEAVEDMODULATORS WITHREDUCED COMPLEXITY175 6.4SIMULATIONS182 6.5IMPLEMENTATIONISSUES184 6.5.1Finite Opamp Gain184 6.5.2Opamp dc Offset185 6.5.3Mismatch Effects187 6.5.4Sampling Clock Jitter190 6.5.5Critical Delay Problem190 HARDWARE COMPARISON 6.6192 6.7HIGHERORDERTIMEINTERLEAVEDMODULATORS194 6.7.1Cascaded Integrators with FeedForward Summation Topology 195 6.7.2Cascaded Integrators with Distributed Feedback as well as Feedforward Branch Topology199 6.7.3Simulations201 6.7.4Coefficient Mismatches203 6.8ZEROINSERTIONINTERPOLATIONTIMEINTERLEAVING206 6.9FURTHERPRACTICALISSUES215 6.9.1Sampling Clock Jitter Effects215 6.9.2Branch Mismatch Effects217 6.10CONCLUSION218
References
221