Power-Constrained Testin of VLSI Circuts

Power-Constrained Testin of VLSI Circuts




Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density. Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.



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Published 21 January 2013
Reads 4
EAN13 0306487314
License: All rights reserved
Language English

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Foreword Preface Acknowledgments
1.DESIGN AND TEST OF DIGITAL INTEGRATED CIRCUITS 1.1Introduction 1.2VLSI Design Flow 1.3External Testing Using Automatic Test Equipment 1.4Internal Testing Using BuiltIn SelfTest 1.5Power Dissipation During Test Application 1.6Organization of the Book 2.POWER DISSIPATION DURING TEST 2.1Introduction 2.2Test Power Modeling and Preliminaries 2.3Power Concerns During Test 2.4Sources of Higher Power Dissipation During Test Application 2.5Summary 3.APPROACHES TO HANDLE TEST POWER 3.1Introduction 3.2A Taxonomy of the Existing Approaches for PowerConstrained Testing 3.3Test Set Dependent vs. Test Set Independent Approaches 3.4TestperScanTestperClock vs. 3.5External TestInternal Test vs. 3.6Multiple Test Sources and SinksSingle vs. 3.7PowerConstrained Test Scheduling 3.8Summary
v ix xi
1 1 2 4 7 17 19 21 21 22 25 26 30 31 31
31 34 37 38 46 46 49
BEST PRIMARY INPUT CHANGE TIME 4.1Introduction 4.2Scan Cell and Test Vector Reordering 4.3A Technique for Power Minimization 4.4Algorithms for Power Minimization 4.5Experimental Results 4.6Summary MULTIPLE SCAN CHAINS 5.1Introduction 5.2Multiple Scan ChainBased DFT Architecture 5.3Multiple Scan Chains Generation 5.4Experimental Results 5.5Summary POWERCONSCIOUS TEST SYNTHESIS AND SCHEDULING 6.1Introduction 6.2Power Dissipation in BIST Data Paths 6.3Effect of Test Synthesis and Scheduling 6.4PowerConscious Test Synthesis and Scheduling Algorithm 6.5Experimental Results 6.6Summary
7.POWER PROFILE MANIPULATION 7.1Introduction 7.2The Global Peak Power Approximation Model 7.3Power Profile Manipulation 7.4PowerConstrained Test Scheduling 7.5Experimental Results 7.6Summary 8.CONCLUSION References About the Authors Index
51 51 52 55 68 73 85 87 87 88 97 104 111
113 113 115 117 124 132 137
139 139 139 141 147 153 156
159 163 175 177