Reuse Methodology Manual for System-on-a-Chip Design Third Edition

Reuse Methodology Manual for System-on-a-Chip Design Third Edition




Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in an SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come.
Development methodology necessarily differs between system designers and processor designers, as well as between DSP developers and chipset developers. However, there is a common set of problems facing everyone who is designing complex chips.
In response to these problems, design teams have adopted a block-based design approach that emphasizes design reuse. Reusing macros (sometimes called "cores") that have already been designed and verified helps to address all of the problems above. However, in adopting reuse-based design, design teams have run into a significant problem. Reusing blocks that have not been explicitly designed for reuse has often provided little or no benefit to the team. The effort to integrate a pre-existing block into new designs can become prohibitively high, if the block does not provide the right views, the right documentation, and the right functionality.
From this experience, design teams have realized that reuse-based design requires an explicit methodology for developing reusable macros that are easy to integrate into SoC designs. This manual focuses on describing these techniques.
Features of the Third Edition:
Up to date;
State of the art;
Reuse as a solution for circuit designers;
A chronicle of "best practices";
All chapters updated and revised;
Generic guidelines&endash;non tool specific;
Emphasis on hard IP and physical design.



Published by
Published 01 January 2002
Reads 9
EAN13 0306476401
License: All rights reserved
Language English

Legal information: rental price per page €. This information is given for information only in accordance with current legislation.

Report a problem
Table of Contents
Preface to the Third Edition
1Introduction 1.1Goals of This Manual 1.1.1Assumptions 1.1.2Definitions 1.1.3 Virtual Socket Interface Alliance 1.2Design for Reuse: The Challenge 1.2.1Design for Use 1.2.2Design for Reuse 1.3The Emerging Business Model for Reuse
2The SystemonChip Design Process 2.1A Canonical SoC Design 2.2System Design Flow 2.2.1Waterfall vs. Spiral 2.2.2TopDown vs. BottomUp 2.2.3Construct by Correction 2.2.4Summary
1 2 3 3 4 4 5 5 6
9 9 11 11 15 15 16
The Specification Problem 2.3.1Specification Requirements 2.3.2Types of Specifications The System Design Process
Reuse Methodology Manual
SystemLevel Design Issues: Rules and Tools 3.1The Standard Model 3.1.1Soft IP vs. Hard IP 3.1.2The Role of FullCustom Design in Reuse 3.2Design for Timing Closure: Logic Design Issues 3.2.1Interfaces and Timing Closure 3.2.2Synchronous vs. Asynchronous Design Style 3.2.3Clocking 3.2.4Reset 3.2.5Timing Exceptions and Multicycle Paths 3.3Design for Timing Closure: Physical Design Issues 3.3.1Floorplanning 3.3.2Synthesis Strategy and Timing Budgets 3.3.3Hard Macros 3.3.4Clock Distribution 3.4Design for Verification: Verification Strategy 3.5System Interconnect and OnChip Buses 3.5.1Basic Interface Issues 3.5.2Tristate vs. Mux Buses 3.5.3Synchronous Design of Buses 3.5.4Summary 3.5.5IPtoIP Interfaces 3.6Design for BringUp and Debug: OnChip Debug Structures 3.7Design for Low Power 3.7.1Lowering the Supply Voltage 3.7.2Reducing Capacitance and Switching Activity 3.7.3Sizing and Other Synthesis Techniques 3.7.4Summary 3.8Design for Test: Manufacturing Test Strategies 3.8.1SystemLevel Test Issues 3.8.2 Memory Test 3.8.3Microprocessor Test 3.8.4Other Macros 3.8.5Logic BIST
17 17 18 19
23 23 25 27 28 28 33 35 36 37 38 38 39 39 40 40 42 43 47 47 47 48 51 52 53 54 56 57 57 57 58 58 59 59
Reuse Methodology Manual
Prerequisites for Reuse 3.9.1Libraries 3.9.2Physical Design Rules
The Macro Design Process 4.1 Overview of IP Design 4.1.1Characteristics of Good IP 4.1.2Implementation and Verification IP 4.1.3Overview of Design Process 4.2Key Features 4.3 Planning and Specification 4.3.1 Functional Specification 4.3.2 Verification Specification 4.3.3 Packaging Specification 4.3.4Development Plan 4.3.5HighLevel Models as Executable Specifications 4.4Macro Design and Verification 4.4.1Summary 4.5 Soft Macro Productization 4.5.1Productization Process 4.5.2Activities and Tools
RTL Coding Guidelines 5.1 Overview of the Coding Guidelines 5.2 Basic Coding Practices 5.2.1General Naming Conventions 5.2.2Naming Conventions for VITAL Support 5.2.3State Variable Names 5.2.4Include Informational Headers in Source Files 5.2.5Use Comments 5.2.6Keep Commands on Separate Lines 5.2.7Line Length 5.2.8 Indentation 5.2.9Do Not Use HDL Reserved Words 5.2.10 Port Ordering 5.2.11 Port Maps and Generic Maps 5.2.12 VHDL Entity, Architecture, and Configuration Sections 5.2.13 Use Functions 5.2.14 Use Loops and Arrays 5.2.15Use Meaningful Labels
60 60 61
63 63 64 65 67 68 69 69 71 71 71 72 73 77 78 78 78
81 81 82 82 84 85 85 87 87 87 88 89 89 92 93 93 94 96
Reuse Methodology Manual
Coding for Portability 5.3.1Use Only IEEE Standard Types (VHDL) 5.3.2Do Not Use HardCoded Numeric Values 5.3.3Packages (VHDL) 5.3.4Constant Definition Files (Verilog) 5.3.5Avoid Embedding Synthesis Commands 5.3.6Use TechnologyIndependent Libraries 5.3.7Coding For Translation Guidelines for Clocks and Resets 5.4.1Avoid Mixed Clock Edges 5.4.2Avoid Clock Buffers 5.4.3Avoid Gated Clocks 5.4.4Avoid Internally Generated Clocks 5.4.5Gated Clocks and LowPower Designs 5.4.6Avoid Internally Generated Resets 5.4.7Reset Logic Function 5.4.8SingleBit Synchronizers 5.4.9 MultipleBit Synchronizers Coding for Synthesis 5.5.1Infer Registers 5.5.2Avoid Latches 5.5.3If you must use a latch 5.5.4Avoid Combinational Feedback 5.5.5Specify Complete Sensitivity Lists 5.5.6Blocking and Nonblocking Assignments (Verilog) 5.5.7Signal vs. Variable Assignments (VHDL) 5.5.8Case Statements vs. ifthenelse Statements 5.5.9Coding Sequential Logic 5.5.10Coding Critical Signals 5.5.11Avoid Delay Times 5.5.12Avoid full_case and parallel_case Pragmas Partitioning for Synthesis 5.6.1Register All Outputs 5.6.2Locate Related Combinational Logic in a Single Module 5.6.3Separate Modules That Have Different Design Goals 5.6.4Asynchronous Logic 5.6.5Arithmetic Operators: Merging Resources 5.6.6Partitioning for Synthesis Runtime 5.6.7Avoid Timing Exceptions 5.6.8 Eliminate Glue Logic at the Top Level. 5.6.9ChipLevel Partitioning
97 97 98 98 98 99 99 100 101 102 103 103 104 105 106 107 108 108 108 109 110 113 113 114 117 119 120 122 124 124 124 125 125 126 127 128 128 130 130 133 134
Reuse Methodology Manual
5.7 5.8
Designing with Memories Code Profiling
Macro Synthesis Guidelines 6.1Overview of the Synthesis Problem 6.2Macro Synthesis Strategy 6.2.1 Macro Timing Constraints 6.2.2 Subblock Timing Constraints 6.2.3 Synthesis in the Design Process 6.2.4 Subblock Synthesis Process 6.2.5 Macro Synthesis Process 6.2.6 Wire Load Models 6.2.7 Preserve Clock and Reset Networks 6.2.8 Code Checking Before Synthesis 6.2.9 Code Checking After Synthesis 6.3Physical Synthesis 6.3.1 Classical Synthesis 6.3.2 Physical Synthesis 6.3.3 Physical Synthesis Deliverables 6.4RAM and Datapath Generators 6.4.1 Memory Design 6.4.2 RAM Generator Flow 6.4.3 Datapath Design 6.5Coding Guidelines for Synthesis Scripts
Macro Verification Guidelines 7.1Overview of Macro Verification 7.1.1 Verification Plan 7.1.2 Verification Strategy 7.2Inspection as Verification 7.3Adversarial Testing 7.4Testbench Design 7.4.1 TransactionBased Verification 7.4.2ComponentBased Verification 7.4.3 Automated Response Checking 7.4.4 Verification Suite Design 7.5Design of Verification Components 7.5.1 Bus Functional Models 7.5.2 Monitors
135 136
137 137 138 139 139 140 141 141 142 142 143 143 144 144 145 145 145 146 147 148 150
153 153 154 155 159 160 161 161 163 165 166 169 169 171
7.5.3Device Models 7.5.4Verification Component Usage Getting to 100% 7.6.1Functional and Code Coverage 7.6.2Prototyping 7.6.3Limited Production 7.6.4Property Checking 7.6.5Code Coverage Analysis Timing Verification
Reuse Methodology Manual
171 172 172 172 172 173 173 174 177
Developing Hard Macros179 8.1Overview179 8.1.1Why and When to Use Hard Macros180 8.1.2Design Process for Hard vs. Soft Macros181 8.2Design Issues for Hard Macros181 8.2.1FullCustom Design181 8.2.2Interface Design182 8.2.3Design For Test183 8.2.4Clock184 8.2.5Aspect Ratio185 8.2.6Porosity186 8.2.7Pin Placement and Layout187 8.2.8Power Distribution187 8.2.9Antenna Checking188 8.3The Hard Macro Design Process190 8.4Productization of Hard Macros190 8.4.1Physical Design190 8.4.2Verification193 8.5Model Development for Hard Macros194 8.5.1Functional Models194 8.5.2Timing Models199 8.5.3Power Models200 8.5.4Test Models201 8.5.5Physical Models204 8.6Porting Hard Macros204
Macro Deployment: Packaging for Reuse 9.1Delivering the Complete Product 9.1.1Soft Macro Deliverables
207 207 208
Reuse Methodology Manual
9.1.2Hard Macro Deliverables 9.1.3Software 9.1.4The Design Archive Contents of the User Guide
10 System Integration with Reusable Macros 10.1Integration Overview 10.2Integrating Macros into an SoC Design 10.2.1Problems in Integrating IP 10.2.2Strategies for Managing Interfacing Issues 10.2.3Interfacing Hard Macros to the Rest of the Design 10.3Selecting IP 10.3.1Hard Macro Selection 10.3.2Soft Macro Selection 10.3.3Soft Macro Installation 10.3.4Soft Macro Configuration 10.3.5Synthesis of Soft Macros 10.4Integrating Memories 10.5Physical Design 10.5.1Design Planning and Synthesis 10.5.2Physical Placement 10.5.3Timing Closure 10.5.4Verifying the Physical Design 10.5.5Summary
11SystemLevel Verification Issues 11.1The Importance of Verification 11.2The Verification Strategy 11.3 Interface Verification 11.3.1Transaction Verification 11.3.2Data or Behavioral Verification 11.3.3Standardized Interfaces 11.4Functional Verification 11.5Random Testing 11.6ApplicationBased Verification 11.6.1SoftwareDriven Application Testbench 11.6.2Rapid Prototyping for Testing
210 212 213 214
217 217 218 218 219 220 221 221 221 222 223 223 223 224 226 230 234 237 238
239 239 240 241 241 242 244 244 247 249 250 251
Reuse Methodology Manual
11.7GateLevel Verification253 11.7.1SignOff Simulation253 11.7.2Formal Verification254 11.7.3GateLevel Simulation with Full Timing255 11.8Specialized Hardware for System Verification256 11.8.1Accelerated Verification Overview258 11.8.2RTL Acceleration259 11.8.3Software Driven Verification260 11.8.4Traditional InCircuit Verification260 11.8.5Design Guidelines for Emulation 261 11.8.6Testbenches for Emulation261
12Data and Project Management 12.1Data Management 12.1.1Revision Control Systems 12.1.2Bug Tracking 12.1.3Regression Testing 12.1.4Managing Multiple Sites 12.1.5Archiving 12.2Project Management 12.2.1Development Process 12.2.2Functional Specification 12.2.3Project Plan
13Implementing ReuseBased SoC Designs 13.1Alcatel 13.2Atmel 13.3Infineon Technologies 13.4LSI Logic 13.5Philips Semiconductor 13.6STMicroelectronics 13.7Conclusion
265 265 265 267 267 267 268 269 269 269 270
271 272 274 276 278 280 282 284