System Design with SystemC

System Design with SystemC

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English

Description

The emergence of the system-on-chip (SoC) era is creating many new challenges at all stages of the design process. Engineers are reconsidering how designs are specified, partitioned and verified. With systems and software engineers programming in C/C++ and their hardware counterparts working in hardware description languages such as VHDL and Verilog, problems arise from the use of different design languages, incompatible tools and fragmented tool flows.
Momentum is building behind the SystemC language and modeling platform as the best solution for representing functionality, communication, and software and hardware implementations at various levels of abstraction. The reason is clear: increasing design complexity demands very fast executable specifications to validate system concepts, and only C/C++ delivers adequate levels of abstraction, hardware-software integration, and performance. System design today also demands a single common language and modeling foundation in order to make interoperable system--level design tools, services and intellectual property a reality. SystemC is entirely based on C/C++ and the complete source code for the SystemC reference simulator can be freely downloaded from www.systemc.org and executed on both PCs and workstations.
System Design and SystemC provides a comprehensive introduction to the powerful modeling capabilities of the SystemC language, and also provides a large and valuable set of system level modeling examples and techniques. Written by experts from Cadence Design Systems, Inc. and Synopsys, Inc. who were deeply involved in the definition and implementation of the SystemC language and reference simulator, this book will provide you with the key concepts you need to be successful with SystemC. System Design with SystemC thoroughly covers the new system level modeling capabilities available in SystemC 2.0 as well as the hardware modeling capabilities available in earlier versions of SystemC. designed and implemented the SystemC language and reference simulator, this book will provide you with the key concepts you need to be successful with SystemC.
System Design with SystemC will be of interest to designers in industry working on complex system designs, as well as students and researchers within academia. All of the examples and techniques described within this book can be used with freely available compilers and debuggers &endash; no commercial software is needed. Instructions for obtaining the free source code for the examples obtained within this book are included in the first chapter.

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Published by
Published 01 January 2002
Reads 9
EAN13 0306476525
License: All rights reserved
Language English

Legal information: rental price per page €. This information is given for information only in accordance with current legislation.

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Contents
Figures
Foreword
Acknowledgments
1
2
3
Introduction 1.1Motivation 1.2How to Read This Book 1.3History 1.4Modeling Levels 1.5Summary 1.6SystemCResources
Fundamentals of SystemC 2.1Introduction 2.2Time in SystemCModel of 2.3Modules 2.4Interfaces, Ports, and Channels 2.5Processes 2.6Events 2.7Sensitivity 2.8Event Finders 2.9Module and Channel Instantiation 2.10Simulation Semantics 2.11Summary
Models ofComputation 3.1Introduction 3.2ComputationThe “RTL” Model of
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11 11 13 14 16 24 27 29 32 34 37 39
41 41 45
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3.3 3.4 3.5 3.6
CONTENTS
Kahn Process Networks StaticDataflow TransactionLevel Models Summary
Classical Hardware Modeling in SystemC 4.1Introduction 4.2RegisterTransfer Level Modeling 4.3BehavioralLevel Modeling 4.4HardwareOriented DataTypes 4.5Summary
Functional Modeling 5.1Untimed Functional Models – Dataflow 5.2Timed Functional Models 5.3Stopping a Dataflow Simulation 5.4Summary
Parameterized Modules and Channels 6.1Introduction 6.2ParameterizationForms of 6.3Parameterized Designs Examples 6.4Guidelines for Using Parameters in SystemC 6.5Protecting Intellectual Property 6.6Summary
Interface and Channel Design 7.1Introduction 7.2InterfaceDesign 7.3Primitive versus Hierarchical Channels 7.4Primitive Channel Examples 7.5Hierarchical Channel Example 7.6Summary
TransactionLevel Modeling 8.1Introduction 8.2The Simple Bus Design 8.3Structure of the Simple Bus Design 8.4Transaction Interfaces in Simple Bus 8.5Modeling Techniques for High Performance
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87 87 87 89 99 102 107
109 109 109 112 114 121 129
131 131 134 136 138 141
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8.6 8.7 8.8 8.9 8.10 8.11
Overall Execution Scheme within Simple Bus TwoPhase Synchronization Common Questions Executing and Experimenting with the Design Measuring Simulation Performance Summary
CONTENTS
Communication Refinement 9.1Introduction 9.2Steps in the Refinement Process 9.3Hardware–Hardware Communication Refinement 9.4Software–Software Communication Refinement 9.5Hardware–Software Communication Refinement 9.6Summary
10Testbenches, Tracing, and Debugging 10.1Introduction 10.2Testbenches 10.3Tracing 10.4Debugging 10.5Summary
11SystemCConclusions and the Future of 11.1Summary of the Book 11.2SystemCThe Future of 11.3In Conclusion
Bibliography
Index
About the Authors
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