Verilog® Quickstart:  A Practical Guide to Simulation and Synthesis in Verilog, Third Edition

Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, Third Edition

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From a review of the Second Edition
`If you are new to the field and want to know what "all this Verilog stuff is about," you've found the golden goose. The text here is straight forward, complete, and example rich -mega-multi-kudos to the author James Lee. Though not as detailed as the Verilog reference guides from Cadence, it likewise doesn't suffer from the excessive abstractness those make you wade through. This is a quick and easy read, and will serve as a desktop reference for as long as Verilog lives. Best testimonial: I'm buying my fourth and fifth copies tonight (I've loaned out/lost two of my others).'
Zach Coombes, AMD

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Published 01 January 2002
Reads 7
EAN13 0306476800
License: All rights reserved
Language English

Legal information: rental price per page €. This information is given for information only in accordance with current legislation.

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LIST OF FIGURES LIST OF EXAMPLES LIST OF TABLES
1 INTRODUCTION Framing Verilog Concepts The Design Abstraction Hierarchy Types of Simulation Types of Languages Simulation versus Programming HDL Learning Paradigms Where To Get More Information Reference Manuals Usenet Talk Verilog
TABLE OF CONTENTS
2 INTRODUCTION TO THE VERILOG LANGUAGE Identifiers Escaped Identifiers White Space Comments Numbers Text Macros Modules Semicolons Value Set Strengths Numbers, Values, and Unknowns
xii xiv xx
1 3 3 4 4 5 5 7 8 8 8
9 9 10 11 12 12 13 14 14 15 15 16
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3 STRUCTURAL MODELING Primitives Ports Ports in Primitives Ports in Modules Instances Hierarchy Hierarchical Names Connect by Name TopLevel Modules You Are Now Ready To Run Your First Simulations Exercise 1 The Hello Simulation Exercise 2 The 8Bit Hierarchical Adder
Verilog Quickstart
4 BEHAVIORAL MODELING Starting Places for Places for Blocks of Behavioral Code TheinitialKeyword ThealwaysKeyword Delays beginendBlocks forkjoinBlocks System Tasks for Printing Out Results What Is a System Task? $displayand Its Relatives Other Commands To Print Results Writing to Files Setting the Default Radix Exercise 3 Printing Out Results from Wires Buried in the Hierarchy Special Characters Suppressing Spaces in Your Output Data Objects in Verilog Nets Ranges Implicit Nets Registers Memories Initial Value of Regs Integers and Reals Time and Realtime Parameters Events Strings MultiDimensional Arrays Accessing Words and Bits of MultiDimensional Arrays
19 19 20 20 21 21 22 24 26 27 28 28 28
33 34 34 34 35 36 39 47 47 47 49 50 52 53 53 54 57 57 58 59 60 60 61 61 62 63 63 64 64 65
Procedural Assignments Ports and Registers
5 OPERATORS Binary Operators Unary Operators Reduction Operators Ternary Operator Equality Operators Concatenations Logical versus Bitwise Operations Operations That Are Not Legal on Reals Working with Strings Combining Operators Sizing Expressions Signed Operations Signed Constants
6 WORKING WITH BEHAVIORAL MODELING Continuous Assignment Event Control ThealwaysBlock for Combinatorial Logic Event Control Explained TheifStatement ThecaseStatement Exercise 4 Using Expressions andcase Loops TheforeverLoop TherepeatLoop ThewhileLoop TheforLoop Procedural Continuous Assignments tasks functions Exercise 5 Functions and Continuous Assignments A Reminder about Ports and Registers Modeling withinoutPorts Named Blocks ThedisableStatement When is a Simulation Done?
7 USERDEFINED PRIMITIVES
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6 6
5 9
71 71 73 74 75 76 79 80 82 82 83 83 84 84
87 87 91 92 93 97 98 101 107 107 108 109 110 111 116 123 126 126 126 128 128 131
133
viii
Combinatorial UDPs Optimistic Mux Pessimistic Mux The Gritty Details Sequential UDPs UDP Instances The Final Details Exercise 6 Using UDPs
8 PARAMETERIZED MODULES nBit Mux nBit Adder nBymMux nBymRam Using Parameterized Modules Parameter Passing by Name Parameter Passing By Order Parameter Passing by Names List Values of Parameters in Module Instances
9 STATE MACHINES State Machine Types State Machine Modeling Style State Encoding Methods Default Conditions Implicit State Machines Registered and Unregistered Outputs Factors in Choosing a State Machine Modeling Style
10 MODELING TIPS Modeling Combinatorial Logic Combinatorial Models Using Continuous Assignments Combinatorial Models Using thealwaysBlock andregs Combinatorial Models Using Functions Modeling Sequential Logic Sequential Models Usingalways Sequential Models Usinginitial Sequential Models Using tasks Modeling Asynchronous Circuits Modeling a OneShot Modeling Asynchronous Systems SpecialPurpose Models
Verilog Quickstart
134 134 134 135 136 139 139 140
143 144 144 145 146 147 147 147 148 149
151 151 153 161 163 164 165 166
167 167 168 169 172 173 173 173 176 178 178 179 185
TwoDimensional Arrays ZDetectors Multiplier Examples A Proven, Successful Approach to Modeling
11 MODELING STYLE TRADEOFFS Forces That Influence Modeling Style Evolution of a Model Modeling Style and Synthesis Is It Synthesizable? Learning From Other People’s Mistakes When To Use UDPs Blocking and Non Blocking Asssignments
12 TEST BENCHES AND TEST MANAGEMENT Introduction to Testing Model Size versus Test Volume Functional Testing Regression Testing SelfChecking Test Benches SignOff System Test versus Unit Tests ResponseDriven Stimulus Test Benches for Inouts Loading Files into Verilog Memories Test Benches with No Test Vectors Using a Script To Run Test Cases Modeling BIST The Surround and Capture Method
13 COMMON ERRORS Mismatched Ports Missing or Incorrect Declarations Missing Registers Missing Widths Reversed Ranges Improper Use of Procedural Continuous Assignments MissinginitialoralwaysBlocks ZeroDelayalwaysLoops initialInstead ofalways Missing Initialization Overly Complex Code Unintended Storage
ix
185 186 187 197
199 199 200 201 202 203 210 211
213 213 214 215 215 215 220 220 221 224 226 229 229 230 232
237 237 238 238 239 240 240 241 241 242 242 243 243
x
Timing Errors Negative Setup Time ZeroDelay Races
Verilog Quickstart
14 DEBUGGING A DESIGN Overview of Functional Debugging Where Are the Errors? Universal Techniques Printing Out Messages “I am here.” Values The Log File Using Waveforms Interactive Debugging Going Interactive The Prompts Special Keys in Interactive Mode Command History The Key File Traversing and Observing BackTracing FanIn Usingforceandrelease Waveforms, Graphic User Interfaces, and Other Conveniences Catching Problems Later in a Simulation Isolating Differences in Models Summary of Debugging
Appendix A GATE LEVEL DETAILS Primitive Descriptions Logic Gates AND NAND OR NOR XOR XNOR Buffers BUF NOT BUFIF0 BUFIF1 NOTIF0 NOTIF1 PULLDOWN
243 244 244
247 247 248 248 248 248 249 250 250 252 252 253 255 260 263 269 273 274 275 275 277 278
281 281 281 281 282 283 283 284 284 285 285 285 286 286 287 288 288
PULLUP Switches NMOS and RNMOS PMOS and RPMOS CMOS and RCMOS TRAN and RTRAN TRANIF0 and RTRANIF0 TRANIF1 and RTRANIF1 Instance Details Delays Delay Units Printing Out Time and the Timescale Strengths Displaying strengths with%v Strength reduction of switch primitives
Appendix B EXAMPLE SUMMARY
INDEX
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289 289 290 291 292 293 293 294 294 294 295 296 296 297 298
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