Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, Second Edition

Verilog® Quickstart: A Practical Guide to Simulation and Synthesis in Verilog, Second Edition

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Published 01 January 1999
Reads 6
EAN13 0306470489
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Language English

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LIST OF FIGURES LIST OF EXAMPLES LIST OF TABLES
1 INTRODUCTION Framing Verilog Concepts The Design Abstraction Hierarchy Types of Simulation Types of Languages Simulation versus Programming HDL Learning Paradigms Where To Get More Information Reference Manuals Usenet
TABLE OF CONTENTS
2 INTRODUCTION TO THE VERILOG LANGUAGE Identifiers Escaped Identifiers White Space Comments Numbers Text Macros Modules Semicolons Value Set Strengths Numbers, Values, and Unknowns
xiii xv xxi
1 3 3 4 4 5 5 7 8 8
9 9 10 11 12 12 13 14 14 15 15 16
vi
3 STRUCTURAL MODELING Primitives Ports Ports in Primitives Ports in Modules Instances Hierarchy Hierarchical Names Connect by Name TopLevel Modules You Are Now Ready to Run Your First Simulations Exercise 1 The Hello Simulation Exercise 2 The 8Bit Hierarchical Adder
4 STARTING PROCEDURAL MODELING Starting Places for Blocks of Procedural Code The initial Keyword The always Keyword Delays beginend Blocks forkjoin Blocks Summary of Procedural Timing
Verilog Quickstart
5 SYSTEM TASKS FOR DISPLAYING RESULTS What is a System Task? $displayIts Relatives and Other Commands to Print Results Writing to Files Advanced File IO Functions Setting the Default Radix Special Characters The Current Simulation Time Suppressing Spaces in Your Output Periodic Printouts When to Printout Results A Final System Task Exercise 3 Printing Out Results from Wires Buried in the Hierarchy
6 DATA OBJECTS Data Objects in Verilog Nets Ranges
19 19 20 20 21 22 22 24 26 27 28 28 28
33 34 34 34 35 36 39 46
47 47 47 49 51 53 53 54 55 56 58 59 59 59
61 61 61 63
Implicit Nets Ports Regs Memories Initial Value of Regs Integers and Reals Time and Realtime Parameters Events Strings MultiDimensional Arrays Accessing Words and Bits of MultiDimensional Arrays Ports and Regs
7PROCEDURAL ASSIGNMENTS Procedural Assignments, Ports and Regs Best Practices with Procedural Assignments Procedural Assignment for Combinatorial Logic Procedural Assignment for Sequential Logic Philosophy of IntraAssignment Delays for Sequential Assignments Conventions Moving Forward
8 OPERATORS Binary Operators Unary Operators Reduction Operators Ternary Operator Equality Operators Concatenations Logical Versus BitWise Operations Operations That Are Not Legal On Reals Working With Strings Combining Operators Sizing Expressions Signed Operations Signed Constants
vii
64 64 65 65 66 66 67 68 68 69 69 70 70
73 77 78 78 78 79 80
81 81 83 84 85 86 89 91 92 93 93 94 94 95
9 CREATING COMBINATORIAL AND SEQUENTIAL LOGIC97 Continuous Assignment97 Event Control101 The always Block for Combinatorial Logic102 Event Control Explained103
viii
Summary of Procedural Timing
10 PROCEDURAL FLOW CONTROL The if Statement The case Statement Loops Theforever Loop The repeat Loop The while Loop Thefor Loop Exercise 4 Using Expressions and case
11 TASKS AND FUNCTIONS Tasks Automatic Tasks Common Uses for Tasks Functions Functions and Integers Automatic Functions Exercise 5 Functions and Continuous Assignments
12 ADVANCED PROCEDURAL MODELING Using The Event Data Type Procedural Continuous Assignments A Reminder About Ports and Regs Modeling with Inout Ports Named Blocks The Disable Statement When is a Simulation Done?
13 USERDEFINED PRIMITIVES Combinatorial Udps Optimistic Mux Pessimistic Mux The Gritty Details Sequential UDPS UDP Instances The Final Details Exercise 6 Using UDPs
14 PARAMETERIZED MODULES
Verilog Quickstart
106
109 109 110 114 114 115 116 117 118
125 125 129 130 132 134 135 136
137 137 139 144 144 146 146 149
151 152 152 152 153 154 157 157 158
161
NBit Mux NBit Adder NByM Mux NByM Ram Using Parameterized Modules Parameter Passing by Name Parameter Passing by Order Parameter Passing by Named List Values of Parameters in Module Instances
15 STATE MACHINES State Machine Types State Machine Modeling Style State Encoding Methods Default Conditions Implicit State Machines Registered And Unregistered Outputs Factors in Choosing a State Machine Modeling Style
16 MODELING TIPS Modeling Combinatorial Logic Combinatorial Models Using Continuous Assignments Combinatorial Models Using thealwaysBlock andregs Combinatorial Models Using Functions Modeling Sequential Logic Sequential Models Using always Sequential Models Using initial Sequential Models Using Tasks Modeling Asynchronous Circuits Modeling a OneShot Modeling Asynchronous Systems SpecialPurpose Models TwoDimensional Arrays ZDetectors Multiplier Examples A Proven, Successful Approach to Modeling
17 MODELING STYLE TRADEOFFS Forces That Influence Modeling Style Evolution of a Model Modeling Style and Synthesis Is It Synthesizable?
ix
162 162 163 164 165 165 165 166 167
169 169 171 179 181 182 183 185
187 187 188 189 192 193 193 193 196 198 198 199 205 205 206 207 217
219 219 220 221 222
x
Learning From Other People’s Mistakes When To Use Udps Blocking and NonBlocking Assignments
18 TEST BENCHES AND TEST MANAGEMENT Introduction to Testing Model Size versus Test Volume Types of Tests Functional Testing Regression Testing SignOff System Test versus Unit Tests Creating Test Plans The Basic Test Cycle Hardware Setup and Hold and Response Time The Test Cycle for Combinatorial Models The Test Cycle for Sequential Models SelfChecking Test Benches ResponseDriven Stimulus Test Benches for Inouts Loading Files into Verilog Memories Test Benches with No Test Vectors Using A Script To Run Test Cases Modeling Bist The Surround and Capture Method
19 MODEL ORGAINZATION File Organization Declaration Organization ANSI Style ports Testcase Organization Including Test Cases Conditionally Running Rests Model Reuse Summary of Model Orgainzation Compile Directives Predefined Text Macros
20 COMMON ERRORS Mismatched Ports Missing or Incorrect Declarations Missing Regs Missing Widths
Verilog Quickstart
223 230 231
233 233 234 235 235 235 235 236 236 237 238 238 239 241 246 249 251 254 254 255 257
263 263 265 265 266 266 269 269 270 270
271 271 272 272 273
Reversed Ranges Improper Use of Procedural Continuous Assignments Missing initialoralwaysBlocks ZeroDelay always Loops initial Instead ofalways Missing Initialization Overly Complex Code Unintended Storage Timing Errors Negative Setup Time ZeroDelay Races Tool Specific Pragmas
21 DEBUGGING A DESIGN Overview of Functional Debugging Where Are the Errors? Universal Techniques Printing Out Messages “I am here.” Values The Log File Using Waveforms Interactive Debugging Going Interactive The Prompts Special Keys in Interactive Mode Command History The Key File Traversing and Observing BackTracing FanIn Usingforce and release Waveforms, Graphical User Interfaces and Other Conveniences Catching Problems Later in a Simulation Isolating Differences in Models Summary of Debugging
22 CODE COVERAGE Code Coverage and Test Plans Code Coverage and Fifos Code Coverage and State Machines Code Coverage and Modeling Style
xi
274 274 275 275 276 276 277 277 277 278 278 279
281 281 282 282 282 282 283 284 284 286 286 287 289 294 297 303 307 308 309 309 311 312
315 316 319 322 322
xii
Appedix A GATELEVEL DETAILS Primitive Descriptions Logic Gates AND NAND OR NOR XOR XNOR Buffers BUF NOT BUFIF0 BUFIF1 NOTIF0 NOTIF1 PULLDOWN PULLUP Switches NMOS and RNMOS PMOS and RPMOS CMOS and RCMOS TRAN and RTRAN TRANIF0 and RTRANIF0 TRANIF1 and RTRANIF1 Instance Details Delays Delay Units Printing Out Time and the Timescale Strengths Displaying Strengths with %v Strength Reduction of Switch Primitives
INDEX
Verilog Quickstart
325 325 325 325 326 327 327 328 328 329 329 329 330 330 331 332 332 333 333 334 335 336 337 337 338 338 338 339 340 340 341 342
343