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TMS320C24x Evaluation Board Schematic Diagrams

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A-1 Appendix A TMS320C24x Evaluation Board Schematic Diagrams This appendix contains the schematic diagrams for the 'C24x evaluation board Appendix A and TMS320F240 DSP. SPRXE035

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Appendix A
TMS320C24x Evaluation Board
Schematic Diagrams
This appendix contains the schematic diagrams for the 'C24x evaluation board
and TMS320F240 DSP.
SPRXE035 A-1TMS320C24x Evaluation Board Schematic Diagrams
A-2 Schematic Diagram of the TMS320C24x Evaluation Board
TMS320C24x Evaluation Board Schematic Diagrams A-3

Figure A–1.TMS320C24x Evaluation Board
.125 dia., 6 plcs.
6.300
2.100
0.900
3.400
3.350
3.937
2.900
0.650 2.100
0.300 0.225Schematic Diagram of the TMS320C24x Evaluation Board
A-4
Figure A–2.Schematic Diagram of the TMS320C24x Evaluation Board
JP5
VREFLO
3
VREFHI VCC
VDD 2
VCCA
1
R12
D[0..15]
CLKOUT/IOPC1
1 1
8 8 8 1 2 4 6 9 0 2 6 5
33.0 U8
4 5 6 2 3 1 7 2 3 3 1 7 0 0
72 9 D0
ADCIN0/IOPA0
ADCIN0/IOPA0 V V V V V V V V V V V V V V D0
73 10
C R R D D D D D D D D D D C D1
ADCIN1/IOPA1 D1
ADCIN1/IOPA1
74 C E E D D D D D D D D D D C 11 D2
ADCIN2 ADCIN2 D2 A[0..15]
A F F P
75 12 D3
H L
ADCIN3 ADCIN3 D3
76 I O 15 D4
ADCIN4 ADCIN4 D4
77 16 D5
ADCIN5 ADCIN5 D5
78 17 D6
ADCIN6 ADCIN6 D6
79 18 D7
ADCIN7 ADCIN7 D7
91 19 D8
ADCIN8/IOPA3 ADCIN8/IOPA3 D8
90 22 D9
ADCIN9/IOPA2 ADCIN9/IOPA2 D9
89 23
D10
ADCIN10 D10
ADCIN10
88 24 D11
ADCIN11 ADCIN11 D11
83 25 D12
ADCIN12 ADCIN12 D12
82 26 D13
ADCIN13 ADCIN13 D13
81 27 D14 U7
ADCIN14 ADCIN14 D14
80 28 D15 A2 1 12
ADCIN15 ADCIN15 D15 I0 F0 RAMOE–
A3 2 13
I1 F1 RAMWE–
63 110 A0 A15 3 14
ADCSOC/IOPC0 ADCSOC/IOPC0 A0 I2 F2 DAC–
64 111 A1 4 15
CLKOUT/IOPC1 A1 I3 F3 XFER–
65 112 A2 5 16
XF/IOPC2 A2
XF/IOPC2 I4 F4 LEDS–
66 114 A3 6 17
BIO–/IOPC3 BIO/IOPC3 A3 I5 F5 SWITCHES–
67 115 A4 7 18
CAP1/QEP1/IOPC4 CAP1/QEP1/IOPC4 A4 I6 F6
68 116 A5 8 19
CAP2/QEP2/IOPC5 CAP2/QEP2/IOPC5 A5 I7 F7 BUFFEN–
69 117 A6 9
CAP3/IOPC6 CAP3/IOPC6 A6 I8
70 118 A7 11 R56
CAP4/IOPC7 CAP4/IOPC7 A7 I9
119 A8
A8
100 122 A9 503073
PWM7/CMP7/IOPB0 PWM7/CMP7/IOPB0 A9
101 123 A10 R
PWM8/CMP8/IOPB1 PWM8/CMP8/IOPB1 A10
102
124 A11
PWM9/CMP9/IOPB2 A11
PWM9/CMP9/IOPB2 MA15
105 125
A12
T1PWM/T1CMP/IOPB3 T1PWM/T1CMP/IOPB3 A12
106 126 A13 R57
T2PWM/T2CMP/IOPB4 T2PWM/T2CMP/IOPB4 A13
107 127 A14
T3PWM/T3CMP/IOPB5 T3PWM/T3CMP/IOPB5 A14
108 128 A15
TMRDIR/IOPB6 TMRDIR/IOPB6 A15
109 0.0
TMRCLK/IOPB7 TMRCLK/IOPB7
129
DS DS–
44 131
SCITXD/IO SCITXD/IO PS PS–
43 130
SCIRXD/IO SCIRXD/IO IS IS–
45 4
SPISIMO/IO R/W
SPISIMO/IO R/W–
48 6
SPISOMI/IO SPISOMI/IO STRB STRB–
49 1
SPICLK/IO SPICLK/IO WE WE–
51 132
SPISTE/IO SPISTE/IO W/R W/R–
5
BR BR–
36
READY READY
35 94
RS– RS PWM1/CMP1 PWM1/CMP1
37 95
MP/MC– MP/MC PWM2/CMP2 PWM2/CMP2
41 96
PORESET– PORESET PWM3/CMP3 PWM3/CMP3
42 97
PMTMODE
PWM4/CMP4 PWM4/CMP4
56 98
OSCBYP– OSCBYP PWM5/CMP5 PWM5/CMP5
57 99
XTAL2 PWM6/CMP6 PWM6/CMP6
58
XTAL1/CLKIN
32
TRST
40 33
NMI– NMI TMS
53 31
XINT1– XINT1 TDI
54 34
XINT2–/IO XINT2/IO TDO
55 30
XINT3–/IO XINT3/IO V TCK
52 S V V V V V V V V V V V V V 38 P5
PDPINT
PDPINT– EMU0
S S S S S S S S S S S S S S 39
EMU1/OFF 1 2
A S S S S S S S S S S S S S
VCC
3 4
TMS320F240
8 1 2 2 4 6 7 9 1 1 1 5 VCC 5 6
7 3 4 0 9 6 1 1 2 0 1 2 8 9
7 8
4 3 0
9 10
L4 R3
11 12
BEAD
VCC 13 14
10K 1%
U16
8 R7
VCC
R55
VCC
5 JP4
OUT
C45 1 10K 1%
.1uF 4 33 2
GND
3
10Mhz
CLKINSchematic Diagram of the TMS320C24x Evaluation Board
TMS320C24x Evaluation Board Schematic Diagrams A-5
Figure A–2. Schematic Diagram of the TMS320C24x Evaluation Board (Continued)
D[0..15]
U4 U3
A0 4 6 D0 A0 4 6 D8
A0 DQ0 A0 DQ0
A1 3 7 D1 A1 3 7 D9
A1 DQ1 A1 DQ1
A2 2 10 D2 A2 2 10 D10
A2 DQ2 A2 DQ2
A3 1 11 D3 A3 1 11 D11
A3 DQ3 A3 DQ3
A4 32 22 D4 A4 32 22 D12
A4 DQ4 A4 DQ4
A5 31 23 D5 A5 31 23 D13
A5 DQ5 A5 DQ5
A6 30 26 D6 A6 30 26 D14
A6 DQ6 A6 DQ6
A7 29 27 D7 A7 29 27 D15
A7 DQ7 A7 DQ7
A8 21 A8 21
A8 A8
A9 20 A9 20
A9 A9
A10 19 A10 19
A10 A10
A11 18 A11 18
A11 A11
A12 17 A12 17
A12 A12
A13 16 A13 16
A13 A13
A14 15 A14 15
A14 A14
14 14
A15 A15
13 13
A16 A16
28 28
OE OE
12 12
WE WE
5 5
CE CE
SR128KX8RP SR128KX8RP
MA15
DS–
RAMOE–
RAMWE–
A[0..15]
VCC
JP9
R10 3
P6 4.7K 2
HOSTRESET
5 C11 U15 1
9 1 C13
C1+
4 JP11 2
V+
8 1 .1uF 3
C1–
3 2 .1uF
7 3 C10 R60 JP10
2 4 C12 3
C2+
6 6 2
V– BIO–/IOPC3
1 .1uF 5 1.0K 1
C2–
.1uF
DB9F
11 14
SCITXD/IO T1IN T1OUT
10 7
XF/IOPC2 T2IN T2OUT
R11 JP8
13 12 1
R1IN R1OUT
8 9 2
R2IN R2OUT SCIRXD/IO
1.0K 3
MAX232A
SCIRXD/IO*Schematic Diagram of the TMS320C24x Evaluation Board
A-6
Figure A–2. Schematic Diagram of the TMS320C24x Evaluation Board (Continued)
VCCA
BD[0..15]
U13A
VCCA 8
VCCA 3 R30
1
DACOUT1
U11A 2
R34 8 33.0
D[0..15]
1.0K 3 4 TLC2272
U6 1
D0 18 2 BD0 2
B1 A1
D1 17 3 BD1
B2 A2
D2 16 4 BD2 4 TLC2272 R25
B3 A3
D3 15 5 BD3 1
B4 A4
D4 14 6 BD4 D2
B5 A5
D5 13 7 BD5 LM4040DCIM3–2.5 R35 30.1K 1%
B6 A6
D6 12 8 BD6 10K 1% R24
B7 A7
D7 11 9 BD7 2 U11B 10K 1%
B8 A8
19 5
G
1 7
DIR
6
74ACT245 R36 U13B
R18 10K 1% TLC2272
5 R29
U2 7
DACOUT2
D8 18 2 BD8 10K 1% 6
B1 A1
D9 17 3 BD9 33.0
B2 A2
D10 16 4 BD10 R21 TLC2272
B3 A3
D11 15 5 BD11 U9
B4 A4
D12 14 6 BD0 23 36 R22
B5 A5 D0 DVDD VCC
D13 13 7 10K 1% BD1 22 35
B6 A6 D1 AVDD VCCA
D14 12 8 BD2 21
B7 A7 D2
D15 11 9 R20 BD3 20 2 30.1K 1%
B8 A8 D3 VREFA
BD4 19 3 R23
D4 RFBA
19 BD5 18 4 10K 1%
G D5 IOUT1A
1 10K 1% BD6 16 5
DIR D6 IOUT2A
BD7 15
D7
74ACT245 R19 BD8 14 10
D8 VREFB
BD9 13 9
D9 RFBB
BD10 12 8 VCCA
D10 IOUT1B
10K 1% BD11 11 7 U12A
D11 IOUT2B
8
24 3 R33
R/W– VREFC
38 1
25
A0 RFBC DACOUT3
40 26 2
BUFFEN– A1 IOUT1C
27 33.0
IOUT2C
37 4 TLC2272
VCC B1/B2
43 32
WR1 VREFD
44 31 R32
CS RFBD
30
IOUT1D
41 29
XFER IOUT2D
42 30.1K 1%
WR2
33 R31
AGND
34 10K 1%
DGND
MP7680JE
U14 U12B
1 12
CLKOUT/IOPC1 I0 F0
2 13 5 R28
DAC– I1 F1
3 14 7
XFER– I2 F2 DACOUT4
4 15 6
SWRESET I3 F3
5 16 R59 33.0
TRGRESET– I4 F4
A0 6 17 TLC2272
I5 F5 RS–
A1 7 18
I6 F6
8 19 33 R27
HOSTRESET I7 F7 READY
9
XREADY I8
11
I9
30.1K 1%
503074 R26
VCC 10K 1%
A[0..15]
R58
U17 10K 1%
2
VCC VCC
1
RESET PORESET–
4
GND
C27
TL7757CD .1uFSchematic Diagram of the TMS320C24x Evaluation Board
TMS320C24x Evaluation Board Schematic Diagrams A-7
Figure A–2. Schematic Diagram of the TMS320C24x Evaluation Board (Continued)
R47 DS1
330 555–2001
R48 DS2
BD[0..7]
330 555–2001
R49 DS3
330 555–2001
VCC
SW2 U5 U1 R50 DS4
1 16 2 18 BD0 BD0 3 2
A1 B1 D1 Q1
2 15 3 17 BD1 BD1 4 5
A2 B2 D2 Q2
3 14 4 16 BD2 BD2 6 330 555–2001
7
A3 B3 D3 Q3
4 13 5 15 BD3 BD3 8 9
A4 B4 D4 Q4
5 12 6 14 BD4 BD4 13 12
A5 B5 D5 Q5
6 11 7 13 BD5 BD5 14 15
A6 B6 D6 Q6
7 10 8 12 BD6 BD6 17 16 R51 DS5
A7 B7 D7 Q7
8 9 9 11 BD7 BD7 18 19
A8 B8 D8 Q8
SW DIP–8 19 11 330 555–2001
G CLK
R38 R43 1 1
VCC DIR CLR
74ACT245 74HCT273 R52 DS6
10K 1% 10K 1%
R37 R44 330 555–2001
10K 1% 10K 1% R53 DS7
R40 R41
330 555–2001
10K 1% 10K 1%
R54 DS8
R39 R42
330 555–2001
10K 1% 10K 1%
SWITCHES–
VCC VCC VCC
LEDS–
RS–
R4 R5 R6
1.6K 1.6K 1.6K
U10C
VCC DS9
5 6
XF/IOPC2
551–1105
74ACT14 RED
D1 R46 U10B
DL4148 30.1K 1% DS10
3 4
BIO–/IOPC3
R45 551–1205
U10F 74ACT14 YELLOW
33.0 13 12
SWRESET
DS11
SW1 74ACT14
C1 551–1305
4.7uF 20V GREENSchematic Diagram of the TMS320C24x Evaluation Board
A-8
Figure A–2. Schematic Diagram of the TMS320C24x Evaluation Board (Continued)
A[0..15] XREADY
R/W–
W/R–
P3
BR–
A0 A1
1 2 PS–
A2 A3
3 4
A4 A5
5 6
A6 A7
7 8
A8 A9 VCC VCC
9 10
A10 A11 P4
11 12
A12 A13
13 14 1 2
A14 A15
15 16 DS– 3 4
17 18 IS– 5 6
D0 D1
19 20 WE– 7 8
D2 D3
21 22 STRB– 9 10
D4 D5
23 24 11 12
D6 D7
25 26 RS– 13 14 TRGRESET–
D8 D9
27 28 NMI– 15 16 XINT1–
D10 D11
29 30 17 18
D12 D13
31 32 XINT2–/IO 19 20 XINT3–/IO
D14 D15
33 34 21 22
23 24
25 26
27 28
29 30
CLKIN 31 32 CLKOUT/IOPC1
33 34
D[0..15]
VCC VCC
VCCA VCCA P1
P2
1 2
1 2 PWM1/CMP1 3 4 PWM2/CMP2
ADCIN0/IOPA0 3 4 ADCIN1/IOPA1 PWM3/CMP3 5 6 PWM4/CMP4
ADCIN2 5 6 ADCIN3 PWM5/CMP5 7 8 PWM6/CMP6
ADCIN4 7 8 ADCIN5 PWM7/CMP7/IOPB0 9 10 PWM8/CMP8/IOPB1
ADCIN6 9 10 ADCIN7 PWM9/CMP9/IOPB2 11 12 T1PWM/T1CMP/IOPB3
ADCIN8/IOPA3 11 12 ADCIN9/IOPA2 T2PWM/T2CMP/IOPB4 13 14 T3PWM/T3CMP/IOPB5
ADCIN10 13 14 ADCIN11 TMRDIR/IOPB6 15 16 TMRCLK/IOPB7
ADCIN12 15 16 ADCIN13 17 18
17 18 XF/IOPC2 19 20 BIO–/IOPC3
ADCIN14 19 20 ADCIN15 CAP1/QEP1/IOPC4 21 22 CAP2/QEP2/IOPC5
VREFHI 21 22 VREFLO CAP3/IOPC6 23 24 CAP4/IOPC7
23 24 25 26 PDPINT–
DACOUT1 25 26 SCITXD/IO 27 28 SCIRXD/IO*
DACOUT3 27 28 SPISIMO/IO 29 30 SPISOMI/IO
29 30 SPICLK/IO 31 32 SPISTE/IO
31 32 ADCSOC/IOPC0 33 34
33 34
DACOUT4
DACOUT2Schematic Diagram of the TMS320C24x Evaluation Board
TMS320C24x Evaluation Board Schematic Diagrams A-9
Figure A–2. Schematic Diagram of the TMS320C24x Evaluation Board (Continued)
R61
VCC PDPINT–
L1 R62 10K 1%
VCCA BIO–/IOPC3
BEAD 10K 1% R15
XINT1–
C3
4.7uF 20V C25 C36 C40 C41 C42 C43 R13 10K 1%
.1uF .1uF .1uF .1uF .1uF .1uF
XREADY
10K 1% R17
TRGRESET–
L2 R16 10K 1%
RS–
BEAD R2 R1 10.0K 1% R14
3 3 JP2
NMI–
1
C4 2 R9 10K 1%
VREFHI
4.7uF 20V C44 2 2 3
OSCBYP–
.1uF
C35 10K 1% R8
1 10K 1 10K .1uF
MP/MC–
10K 1%
JP3
3
2
VREFLO
1 JP7 JP6
1 3
C32 2 2
.1uF 3 1
J2
ANALOG SW3
JP1
3
2
J1 1
L3
VDD
SW DPDT BEAD
C6 C5
DIGITAL 4.7uF 20V 4.7uF 20V C14 C15 C16 C17 C18 C20 C19 C23 C24 C26
.1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF .1uF
TP1
C2
4.7uF 20V C7 C8 C28 C9 C21 C22 C30
.1uF .1uF .1uF .1uF .1uF .1uF .1uF
VCC
C31 C34 C33 C37 C38 C39
.1uF .1uF .1uF .1uF .1uF .1uF