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1Motorola TMOS Power MOSFET Transistor Device Data

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Niveau: Supérieur, Doctorat, Bac+8
1Motorola TMOS Power MOSFET Transistor Device Data ? N–Channel Enhancement–Mode Silicon Gate This advanced TMOS power FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low voltage, high speed switching applications in power supplies, converters, and PWM motor controls. These devices are particularly well suited for bridge circuits where diode speed and commutating safe operating area are critical and offer additional safety margin against unexpected voltage transients. • Avalanche Energy Specified • Source–to–Drain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–to–Source Voltage VDSS 100 Vdc Drain–to–Gate Voltage (RGS = 1.0 M?) VDGR 100 Vdc Gate–to–Source Voltage — Continuous Gate–to–Source Voltage — Single Pulse (tp ≤ 50 S) VGS VGSM ±20 ±25 Vdc Vdc Drain Current — Continuous Drain Current — Continuous @ 100°C Drain Current — Single Pulse (tp ≤ 10 S) ID ID IDM 14 10 49 Adc Apk Total Power Dissipation @ TC = 25°C Derate above 25°C PD 78 0.63 Watts W/°C Operating and Storage Temperature Range TJ, Tstg –55 to 150 °C UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C) Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C (VDD = 75 V, VGS = 10 V

  • reflects typical

  • characteristics forward

  • tmos power

  • voltage —

  • drain–to–source voltage

  • characteristics

  • switching characteristics

  • forward transconductance


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SEMICONDUCTOR TECHNICAL DATA by IRF530/D

N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
This advanced TMOS power FET is designed to withstand high 14 AMPERES
energy in the avalanche and commutation modes. This new energy 100 VOLTS
efficient design also offers a drain–to–source diode with a fast R = 0.140 DS(on)
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters, and PWM motor
controls. These devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating area
are critical and offer additional safety margin against unexpected
voltage transients.
• Avalanche Energy Specified D
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• I and V Specified at Elevated TemperatureDSS DS(on) G
S
CASE 221A–09
TO-220AB
MAXIMUM RATINGS (T = 25°C unless otherwise noted)C
Rating Symbol Value Unit
Drain–to–Source Voltage V 100 VdcDSS
Drain–to–Gate Voltage (R = 1.0 M ) V 100 VdcGS DGR
Gate–to–Source Voltage — Continuous V ±20 VdcGS
Gate–to–Source Voltage — Single Pulse (t ≤ 50 S) V ±25 Vdcp GSM
Drain Current — Continuous I 14 AdcD
I 10Drain Current — Continuous @ 100°C D
I 49 ApkDrain Current — Single Pulse (t ≤ 10 S) DMp
Total Power Dissipation @ T = 25°C P 78 WattsC D
Derate above 25°C 0.63 W/°C
Operating and Storage Temperature Range T , T –55 to 150 °CJ stg
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (T < 150°C)J
Single Pulse Drain–to–Source Avalanche Energy — STARTING T = 25°C E mJJ AS
(V = 75 V, V = 10 V, PEAK I = 14 A, L = 1.0 mH, R = 25 ) 98DD GS L G
THERMAL CHARACTERISTICS
Thermal Resistance — Junction–to–Case° R 1.60 °C/WJC
Thermal Resistance — Junction–to–Ambient° R 62.5JA
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T 275 °CL
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
E–FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 1
Motorola TMOS Power MOSFET Transistor Device Data 1 Motorola, Inc. 1998

Wq
qELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)J
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage V Vdc(BR)DSS
(V = 0 Vdc, I = 0.25 mAdc) 100 — —GS D
Temperature Coefficient (Positive) — 112 — V/°C
Zero Gate Voltage Drain Current I AdcDSS
(V = 100 Vdc, V = 0 Vdc) — — 10DS GS
(V = 0 Vdc, T = 125°C) — — 100DS GS J
Gate–Body Leakage Current I nAdcGSS
(V = ±20 Vdc, V = 0 Vdc) — — 100GS DS
(1)ON CHARACTERISTICS
(3)Gate Threshold Voltage Cpk ≥ 2.0 V VdcGS(th)
(V = V , I = 0.25 mA) 2.0 2.9 4.0DS GS D
Threshold Temperature Coefficient (Negative) — 6.2 — mV/°C
(3)Static Drain–to–Source On–Resistance Cpk ≥ 2.0 R OhmsDS(on)
(V = 10 Vdc, I = 8.0 Adc) — 0.098 0.140GS D
Drain–to–Source On–Voltage V VdcDS(on)
(V = 10 Vdc, I = 14 Adc) — — —GS D
(V = 8.0 Adc, T = 125°C) — — —GS D J
Forward Transconductance (V = 15 Vdc, I = 8.0 Adc) g 4.0 7.4 — MhosDS D FS
DYNAMIC CHARACTERISTICS
pFInput Capacitance C — 700 800iss
(V = 25 Vdc, V25 Vdc V = 0 Vdc,0 VdcDS GSOutput Capacitance C — 200 500ossff = 1.0 MHz = 1.0 MHz) )
Transfer Capacitance C — 65 150rss
(2)SWITCHING CHARACTERISTICS
Turn–On Delay Time t — 9.0 30 nsd(on)
Rise Time t — 47 75r(V( = 36 Vdc, I36 Vd , I = 8.0 Adc,8 0 Ad ,DS D
V = 10 Vdc, R = 15 )GS GTurn–Off Delay Time t — 33 40d(off)
Fall Time t — 34 45f
Gate Charge Q — 26 40 nCT
Q — 5.0 —(V( = 80 Vdc, I80 Vd , I = 14 Adc,14 Ad , 1DS D
V = 10 Vdc)GS Q — 13 —2
Q — 11 —3
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage V VdcSD
(I = 14 Adc, V = 0 Vdc) — 0.92 1.5S GS
(I = 0 Vdc, T = 125°C) — 0.80 —S GS J
nSReverse Recovery Time t — 103 —rr
t — 78 —a((I = 14 Adc,14 Ad ,S
dI /dt = 100 A/ S)S t — 25 —b
Reverse Recovery Stored Charge Q — 0.46 — CRR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance L nHd
(Measured from the drain lead 0.25″ from package to center of die) — 3.5 —
Internal Source Inductance Ls
(Measured from screw on tab to source bond pad) — 7.5 —
(1) Pulse Test: Pulse Width ≤ 300 S, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
Max limit – Typ(3) Reflects typical values. Cpk
3 sigma
2 Motorola TMOS Power MOSFET Transistor Device Data
WmmTYPICAL ELECTRICAL CHARACTERISTICS
30 30
9 V T = 25°CJ V ≥ 10 VDS T = –55°CJV = 10 V 8 VGS
25 25
25°C 100°C
7 V
20 20
15 15
6 V
10 10
5 V5 5
0 0
013246578910 2 2.53 3.54 4.55 5.56 6.57897.5 8.5
V , DRAIN–TO–SOURCE VOLTAGE (VOLTS) V , GATE–TO–SOURCE VOLTAGE (VOLTS)DS GS
Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics
0.20 0.14
T = 25°CV = 10 V JGS0.18
0.13
T = 100°CJ
0.16
0.12
0.14
0.11
0.12 V = 10 VGS25°C
0.10 0.10
15 V
0.08
0.09
0.06
–55°C 0.08
0.04
0.070.02
0.00 0.06
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 300 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 27.5 30
I , DRAIN CURRENT (AMPS) I , DRAIN CURRENT (AMPS)D D
Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance versus Drain Current
and Temperature and Gate Voltage
10002.0
V = 10 V V = 0 VGS GS1.8
I = 8 AD T = 125°CJ
1.6
1.4 100
100°C1.2
1.0
0.8
10
0.6
0.4
0.2
10
0 10 20 30 40 50 60 70 80 90 100 110–50 –25 0 25 50 75 100 125 150
T , JUNCTION TEMPERATURE (°C) V , DRAIN–TO–SOURCE VOLTAGE (VOLTS)J DS
Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage
Temperature Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data 3

, DRAIN–TO–SOURCE RESISTANCE R , DRAIN–TO–SOURCE RESISTANCE (OHMS) I , DRAIN CURRENT (AMPS)
R
DS(on)
DS(on) D
(NORMALIZED)
R , DRAIN–TO–SOURCE RESISTANCE (OHMS)
I , LEAKAGE (nA)
DS(on)
DSS
I , DRAIN CURRENT (AMPS)
DPOWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted The capacitance (C ) is read from the capacitance curve atiss
by recognizing that the power MOSFET is charge controlled. a voltage corresponding to the off–state condition when cal-
The lengths of various switching intervals ( t) are deter- culating t and is read at a voltage corresponding to thed(on)
mined by how fast the FET input capacitance can be charged on–state when calculating t .d(off)
by current from the generator.
At high switching speeds, parasitic circuit elements com-The published capacitance data is difficult to use for calculat-
plicate the analysis. The inductance of the MOSFET sourceing rise and fall because drain–gate capacitance varies
lead, inside the package and in the circuit wiring which isgreatly with applied voltage. Accordingly, gate charge data is
common to both the drain and gate current paths, produces aused. In most cases, a satisfactory estimate of average input
voltage at the source which reduces the gate drive current.current (I ) can be made from a rudimentary analysis ofG(AV)
the drive circuit so that The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.t = Q/IG(AV)
The MOSFET output capacitance also complicates the
During the rise and fall time interval when switching a resis-
mathematics. And finally, MOSFETs have finite internal gate
tive load, V remains virtually constant at a level known asGS resistance which effectively adds to the resistance of the
the plateau voltage, V . Therefore, rise and fall times maySGP driving source, but the internal resistance is difficult to mea-
be approximated by the following:
sure and, consequently, is not specified.
t = Q x R /(V – V )r 2 G GG GSP The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance ist = Q x R /Vf 2 G GSP
affected by the parasitic circuit elements. If the parasiticswhere
were not present, the slope of the curves would maintain a
V = the gate drive voltage, which varies from zero to VGG GG value of unity regardless of the switching speed. The circuit
R = the gate drive resistance used to obtain the data is constructed to minimize commonG
inductance in the drain and gate circuit loops and is believedand Q and V are read from the gate charge curve.2 GSP
readily achievable with board mounted components. Most
During the turn–on and turn–off delay times, gate current is
power electronic loads are inductive; the data in the figure is
not constant. The simplest calculation uses appropriate val-
taken with a resistive load, which approximates an optimally
ues from the capacitance curves in a standard equation for
snubbed inductive load. Power MOSFETs may be safely op-
voltage change in an RC network. The equations are:
erated into an inductive load; however, snubbing reduces
t = R C In [V /(V – V )]d(on) G iss GG GG GSP switching losses.
t = R C In (V /V )d(off) G iss GG GSP
2200
V = 0 V V = 0 V T = 25°CC DS GS Jiss
2000
1800
1600
1400
1200 Crss
1000
Ciss
800
600
400
Coss
200 Crss
0
10550 101520 25
V VGS DS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4 Motorola TMOS Power MOSFET Transistor Device Data
D
C, CAPACITANCE (pF)V
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
DS
10 80 100
T = 25°CJ
9 QT 72
I = 8 A D
V = 36 V8 V 64 DDGS
tV = 10 V rQ1 Q2 GS7 56
td(off)
6 48
tf
5 40 10 td(on)
4 32
3 24
162 T = 25°CJ
I = 14 AD 81 VQ3 DS
00 1
1 10 1000 2.5517.50 12.515 17.520 22.5 25 27.5
Q , TOTAL GATE CHARGE (nC) R , GATE RESISTANCE (OHMS)G G
Figure 8. Gate–To–Source and Drain–To–Source Figure 9. Resistive Switching Time
Voltage versus Total Charge Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
14
V = 0 VGS
12 T = 25°CJ
10
8
6
4
2
0
0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
V , SOURCE–TO–DRAIN VOLTAGE (VOLTS)SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define able operation, the stored energy from circuit inductance dis-
the maximum simultaneous drain–to–source voltage and sipated in the transistor while in avalanche must be less than
drain current that a transistor can handle safely when it is for- the rated limit and adjusted for operating conditions differing
ward biased. Curves are based upon maximum peak junc- from those specified. Although industry practice is to rate in
tion temperature and a case temperature (T ) of 25°C. PeakC terms of energy, avalanche energy capability is not a con-
repetitive pulsed power limits are determined by using the stant. The energy rating decreases non–linearly with an in-
thermal response data in conjunction with the procedures
crease of peak current in avalanche and peak junction
discussed in AN569, Transient Thermal Resistance–General
temperature.
Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
Switching between the off–state and the on–state may tra-
to–source avalanche at currents up to rated pulsed currentverse any load line provided neither rated peak current (I )DM
(I ), the energy rating is specified at rated continuous cur-DMnor rated voltage (V ) is exceeded and the transition timeDSS
rent (I ), in accordance with industry custom. The energy rat-D(t ,t ) do not exceed 10 s. In addition the total power aver-r f
ing must be derated for temperature as shown in theaged over a complete switching cycle must not exceed
accompanying graph (Figure 12). Maximum energy at cur-(T – T )/(R ).J(MAX) C JC
rents below rated continuous I can safely be assumed toA Power MOSFET designated E–FET can be safely used D
in switching circuits with unclamped inductive loads. For reli- equal the values indicated.
Motorola TMOS Power MOSFET Transistor Device Data 5
qm
V , GATE–TO–SOURCE VOLTAGE (VOLTS)
GS
, SOURCE CURRENT (AMPS)
I
S
t, TIME (ns)SAFE OPERATING AREA
100 110
I = 14 AV = 20 V DGS 100
SINGLE PULSE
10 s 90
T = 25°CC
80
10
70100 s
601ms
50
10 ms
40
1.0 dc
30
R LIMIT 20DS(on)
THERMAL LIMIT
10
PACKAGE LIMIT
00.1
0.1 1.0 10 100 1000 25 50 75 100 125 150
V , DRAIN–TO–SOURCE VOLTAGE (VOLTS) T , STARTING JUNCTION TEMPERATURE (°C)DS J
Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P(pk)0.1 0.05 R (t) = r(t) RJC JC
D CURVES APPLY FOR POWER0.02
PULSE TRAIN SHOWN
t READ TIME AT t0.01 1 1
t T – T = P R (t)2 J(pk) C (pk) JCSINGLE PULSE
DUTY CYCLE, D = t /t1 2
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
t ta b
TIME
0.25 It Sp
IS
Figure 14. Diode Reverse Recovery Waveform
6 Motorola TMOS Power MOSFET Transistor Device Data
mqmqq
I , DRAIN CURRENT (AMPS)
D
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
E
, SINGLE PULSE DRAIN–TO–SOURCE
AS
AVALANCHE ENERGY (mJ)PACKAGE DIMENSIONS
NOTES:
SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI–T– PLANE
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.C
3. DIMENSION Z DEFINES A ZONE WHERE ALL
T S BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
DIM MIN MAX MIN MAXAQ
A 0.570 0.620 14.48 15.75
B 0.380 0.405 9.66 10.2812 3 U
C 0.160 0.190 4.07 4.82
D 0.025 0.035 0.64 0.88H
F 0.142 0.147 3.61 3.73
K G 0.095 0.105 2.42 2.66
H 0.110 0.155 2.80 3.93Z
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
L R
N 0.190 0.210 4.83 5.33
Q 0.100 0.120 2.54 3.04V J
R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39G
T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
V 0.045 ––– 1.15 –––N
Z ––– 0.080 ––– 2.04
CASE 221A–09
(TO–220AB)
ISSUE Z
Motorola TMOS Power MOSFET Transistor Device Data 7