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74AC374 OCTAL D TYPE FLIP FLOP

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Description

Niveau: Supérieur, Doctorat, Bac+8
74AC374 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING April 1997 n HIGH SPEED: n fMAX = 270 MHz (TYP.) at VCC = 5V n LOW POWER DISSIPATION: ICC = 8 µA (MAX.) at TA = 25 oC n HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) n 50? TRANSMISSION LINE DRIVING CAPABILITY n SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL =24 mA (MIN) n BALANCED PROPAGATION DELAYS: tPLH ? tPHL n OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V n PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 n IMPROVED LATCH-UP IMMUNITY DESCRIPTION The AC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. These 8 bit D-Type flip-flops are controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.

  • low

  • output current

  • clock clock

  • dc input

  • test conditions

  • circuit pin

  • state output

  • absolute maximum

  • high


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Language English
74AC374 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING
nHIGH SPEED: nfMAX= 270 MHz (TYP.) at VCC= 5V nLOW POWER DISSIPATION: o ICC= 8mA (MAX.) at TA= 25 C nHIGH NOISE IMMUNITY: VNIH= VNIL= 28% VCC(MIN.) n50WTRANSMISSION LINE DRIVING CAPABILITY nSYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL= 24 mA (MIN) nBALANCED PROPAGATION DELAYS: tPLH4tPHL nOPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 6V nPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 nIMPROVED LATCH-UP IMMUNITY
DESCRIPTION The AC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal 2 wiring C MOS technology. It is ideal for low power applications mantaining high speed operation similar to equivalent Bipolar Schottky TTL. These 8 bit D-Type flip-flops are controlled by a
PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1997
B M (Plastic Package) (Micro Package) ORDER CODES : 74AC374B 74AC374M
clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
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