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Data Sheet No PD60172 E

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Description

Niveau: Supérieur, Doctorat, Bac+8
Data Sheet No. PD60172-E Typical Connection HIGH AND LOW SIDE DRIVER Features • Floating channel designed for bootstrap operation Fully operational to +600V Tolerant to negative transient voltage dV/dt immune • Gate drive supply range from 10 to 20V • Undervoltage lockout for both channels • 3.3V and 5V input logic compatible • Matched propagation delay for both channels • Logic and power ground +/- 5V offset. • Lower di/dt gate driver for better noise immunity • Output source/sink current capability 1.4A/1.8A IR21814 IR2181 IR2181(4)(S) Packages 1 VCC VB VS HO LOCOM HIN LIN up to 600V TO LOAD VCC LIN HIN up to 600V TO LOAD VCC VB VS HO LO COM HIN VSS LIN VCC VSS LIN HIN (Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. Description The IR2181(4)(S) are high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output channels. Pro- prietary HVIC and latch immune CMOS technologies enable rugge- dized monolithic construction.

  • logic fixed supply

  • current —

  • driver output

  • vcc low

  • vss

  • high side

  • output voltage

  • side floating


Subjects

Informations

Published by
Reads 9
Language English

1

LOTAOD

up to 600V

IR21814

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Data Sheet No. PD60172-E

LTOOAD
OHVVBCCVNIHSNILV
SS
COM
OL

IR2181
(
4
)(S)
HIGH AND LOW SIDE DRIVER
FeaturesPackages

Floating channel designed for bootstrap operation
Fully operational to +600V
14-Lead PDIP
Tolerant to negative transient voltage
IR21814
dV/dt immune
8-Lead SOIC

Gate drive supply range from 10 to 20V
IR2181S

Undervoltage lockout for both channels

3.3V and 5V input logic compatible

Matched propagation delay for both channels
8-Lead PDIP

Logic and power ground +/- 5V offset.
IR2181

Lower di/dt gate driver for better noise immunity
14I-RL2e1a8d 1S4OSIC

Output source/sink current capability 1.4A/1.8A
Description
IR2181/IR2183/IR2184 Feature Comparison
The IR2181(4)(S) are high voltage,
high speed power MOSFET and IGBT
drivers with independent high and low
side referenced output channels. Pro-
prietary HVIC and latch immune
CMOS technologies enable rugge-
dized monolithic construction. The
logic input is compatible with standard
CMOS or LSTTL output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage
designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power
MOSFET or IGBT in the high side configuration which operates up to 600 volts.
Typical Connection
up to 600V
VCCVVHIN
H
C
I
C
NHO
B
LIN
LINV
S
MOCOLIR2181
V
H
C
IN
C
NIL(Refer to Lead Assignments for correct pin
ecloencftirgicurala tcioonn)n. eTchtiiso/nTsh oensley . d iPalgeraasme( rse) fserh toow
V
SS
poruor pAepr pcliirccautiito bn oNarodt elsa yaonudt. DesignTips for

I% &$+558IK#+"*=HCH2IAO,5"1""& +I#
=HAJ1"& I &+558IK#+"*=HCH2IAO"1#"10"!& +I#
=HAJ1!& I &+558A"1#"10"& +& BB66IE2@KH/AE6@=A,?EC
EJALAHFEJ?K@?IH+?EC
JKF1JH=2
IR2181
(
4
) (S)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
SymbolDefinitionMin.Max.Units
V
B
High side floating absolute voltage-0.3625
V
S
High side floating supply offset voltageV
B
- 25V
B
+ 0.3
V
HO
High side floating output voltageV
S
- 0.3V
B
+ 0.3
V
CC
Low side and logic fixed supply voltage-0.325V
V
LO
Low side output voltage-0.3V
CC
+ 0.3
V
IN
Logic input voltage (HIN & LIN - IR2181/IR21814) V
SS
- 0.3 V
SS
+ 10
V
SS
Logic ground (IR21814 only)V
CC
- 25V
CC
+ 0.3
dV
S
/dtAllowable offset supply voltage transient50V/ns
P
D
Package power dissipation @ T
A


+25°C(8-lead PDIP)1.0
(8-lead SOIC)0.625
(14-lead PDIP)1.6W
(14-lead SOIC)1.0
Rth
JA
Thermal resistance, junction to ambient(8-lead PDIP)125
(8-lead SOIC)200°C/W
(14-lead PDIP)75
(14-lead SOIC)120
T
J
Junction temperature150
T
S
Storage temperature-50150°C
T
L
Lead temperature (soldering, 10 seconds)300
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The V
S
and V
SS
offset rating are tested with all supplies biased at 15V differential.
SymbolDefinitionMin.Max.Units
VBHigh side floating supply absolute voltageV
S
+ 10V
S
+ 20
V
S
High side floating supply offset voltageNote 1600
V
HO
High side floating output voltageV
S
V
B
V
CC
Low side and logic fixed supply voltage1020V
V
LO
Low side output voltage0V
CC
V
IN
Logic input voltage (HIN & LIN - IR2181/IR21814) V
SS
V
SS
+ 5
V
SS
Logic ground (IR21814/IR21824 only)-55
T
A
Ambient temperature-40125°C
Note 1: Logic operational for V
S
of -5 to +600V. Logic state held for V
S
of -5V to -V
BS
. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: HIN and LIN pins are internally clamped with a 5.2V zener diode.
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IR2181
(
4
) (S)

Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, V
SS
= COM, C
L
= 1000 pF, T
A
= 25°C.
SymbolDefinition Min. Typ.Max.UnitsTest Conditions
tonTurn-on propagation delay180270V
S
= 0V
toffTurn-off propagation delay220330V
S
= 0V or 600V
MTDelay matching, HS & LS turn-on/off035nsec
trTurn-on rise time4060V
S
= 0V
tfTurn-off fall time2035V
S
= 0V

Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15V, V
SS
= COM and T
A
= 25°C unless otherwise specified. The V
IL
, V
IH
and I
IN
parameters are
rreeffeerreenncceedd ttoo CVO
SS
M/ CaOndM aaren da parpeli caapbpllei ctao btlhe et or etshpe ercetisvpee cotuivtpe uitn lpeuat dlse: aHdsO HaInNd aLnOd. LIN. The V
O
, I
O
and Ron parameters are
SymbolDefinitionMin.Typ.Max.UnitsTest Conditions
V
IH
Logic 1 input voltag(eI R2181/IR21814 ) 2.7 V
CC
= 10V to 20V
V
IL
Logic 0 input voltag(eI R2181/IR21814) 0.8 V V
CC
= 10V to 20V
V
OH
High level output voltage, V
BIAS
- V
O
1.2I
O
= 0A
V
OL
Low level output voltage, V
O
0.1I
O
= 0A
I
LK
Offset supply leakage current50V
B
= V
S
= 600V
I
QBS
Quiescent V
BS
supply current2060150V
IN
= 0V or 5V
I
QCC
Quiescent V
CC
supply current50120240µAV
IN
= 0V or 5V
I
IN+
Logic 1 input bias current 25 60V
IN
= 5V
I
IN-
Logic 0 input bias current 1.0V
IN
= 0V
V
CCUV+
V
CC
and V
BS
supply undervoltage positive going8.08.99.8
V
BSUV+
threshold
V
CCUV-
V
CC
and V
BS
supply undervoltage negative going7.48.29.0V
V
BSUV-
threshold
V
CCUVH
Hysteresis0.30.7
V
BSUVH
I
O+
Output high short circuit pulsed current1.41.9V
O
= 0V,
APW

10 µs
I
O-
Output low short circuit pulsed current1.82.3V
O
= 15V,
PW

10 µs

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3

IR2181
(
4
) (S)

Functional Block Diagrams

4

NIH

NIL

NIH

NILVSS

VU 2181
DETECT
RHVPULSERQ
LEVELFILTERS
VSS/COMSHIFTER
LEVELPULSE
SHIFTGENERATOR

21814

VSS/COM
LEVELDELAY
TFIHS

VUDETECT

VUDETECT
RHVPULSERQ
LEVELFILTERS
VSS/COMSHIFTER
LEVELPULSE
SHIFTGENERATOR

VSS/COM
LEVELDELAY
TFIHS

VUDETECT

BVOHVS

CCVOLMOC

BVOHSV

CCVOLCMO

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IR2181
(
4
) (S)

Lead Definitions
SymbolDescription
HINLogic input for high side gate driver output (HO), in phase (IR2181/IR21814)
LINLogic input for low side gate driver output (LO), in phase (IR2181/IR21814)
VSSLogic Ground (IR21814 only)
V
B
High side floating supply
HOHigh side gate drive output
V
S
High side floating supply return
V
CC
Low side and logic fixed supply
LOLow side gate drive output
COMLow side return

Lead Assignments

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1HINVB
8
2LINHO7
3COMVS6
4LOVCC5
8-Lead PDIP
IR2181

1HIN
1
4
2LINVB13
3VSSHO12
V11S45COM10
9OL68V7CC14-Lead PDIP
IR21814

1HINVB
8
2LINHO7
3COMVS6
4LOVCC5
8-Lead SOIC
IR2181S

1HIN
1
4
2LINVB13
3VSSHO12
1V14S5COM10
96OL87VCC14-Lead SOIC
IR21814S

5

IR2181
(
4
) (S)

Case outlines

6

8-Lead PDIP

BDA5
FOOTPRINT
8X 0.72 [.028]
68765H
E12340.25 [.010] A
6.46 [.255]

01-3003 01
(MS
0
-
1
0
-
0
6
1
0
A
1
B
4
)

DIMINCHESMILLIMETERS
MINMAXMINMAX
A.0532.06881.351.75
A1.0040.00980.100.25
b.013.0200.330.51
c.0075.00980.190.25
D.189.19684.805.00
E.1497.15743.804.00
e.050 BASIC1.27 BASIC
e1.025 BASIC0.635 BASIC
H.2284.24405.806.20
K.0099.01960.250.50
L.016.0500.401.27
y 0
°
8
°
0
°
8
°

6Xe
3X 1.27 [.050]8X 1.78 [.070]
e1K x 45
°
ACyA10.10 [.004] 8X L8X c
b X80.25 [.010] CAB7
NOTES:5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
2. CONTROLLING DIMENSION: MILLIMETER6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES]. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.

01-6027
8-Lead SOIC
01-0021 11

(MS-012AA)
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14-Lead PDIP

14-Lead SOIC (narrow body)

IR2181
(
4
) (S)

01-6010
01-3002 03
(MS-001AC)

01-6019
01-3063 00
(MS-012AB)

7

IR2181
(
4
) (S)

8

NIHNILOHOLFigure 1. Input/Output Timing Diagram

HIN
50%50%
NIL

OLOH%01TMTM%09OLOHFigure 3. Delay Matching Waveform Definitions

HIN
50%50%
NILtontrtofftf
90%90%
OHLO
10%10%
Figure 2. Switching Time Waveform Definitions

IR WORLD HEADQUART

E

R

S

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