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MOTOROLA CMOS LOGIC DATA

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Niveau: Supérieur, Doctorat, Bac+8
MOTOROLA CMOS LOGIC DATA 45 MC14013B ! The MC14013B dual type D flip–flop is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each flip–flop has independent Data, (D), Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip–flops for counter and toggle applications. • Static Operation • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Logic Edge–Clocked Flip–Flop Design Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive–going edge of the clock pulse • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range • Pin–for–Pin Replacement for CD4013BÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) ÎÎÎÎ Symbol ÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎ Value ÎÎ Unit ÎÎÎÎ VDD ÎÎÎÎÎÎÎÎÎÎ DC Supply Voltage ÎÎÎÎÎ – 0.5 to + 18.0 ÎÎ V ÎÎÎÎ Vin, Vout ÎÎÎÎÎÎÎÎÎÎ Input or Output Voltage (DC or Transient) ÎÎÎÎÎ – 0.5 to VDD + 0.5 ÎÎ V ÎÎÎÎ lin, lout ÎÎÎÎÎÎÎÎÎÎ Input or Output Current (DC or Transient), per Pin ÎÎÎÎÎ ± 10 ÎÎ mA ÎÎÎÎ PD ÎÎÎÎÎÎÎÎÎÎ Power Dissipation, per Package† ÎÎÎÎÎ 500 ÎÎ mW

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  • unused outputs

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  • plastic dip

  • clock† data


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SEMICONDUCTOR TECHNICAL DATA
L SUFFIXThe MC14013B dual type D flip–flop is constructed with MOS P–channel
CERAMICand N–channel enhancement mode devices in a single monolithic structure.
CASE 632
Each flip–flop has independent Data, (D), Direct Set, (S), Direct Reset, (R),
and Clock (C) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flip–flops for counter and
P SUFFIXtoggle applications.
PLASTIC
• Static Operation CASE 646
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Edge–Clocked Flip–Flop Design D SUFFIX
Logic state is retained indefinitely with clock level either high or low; SOIC
information is transferred to the output only on the positive–going edge CASE 751A
of the clock pulse
ORDERING INFORMATION• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range MC14XXXBCP Plastic
MC14XXXBCL Ceramic• Pin–for–Pin Replacement for CD4013B
MC14XXXBD SOIC
T = – 55° to 125°C for all packages.MAXIMUM RATINGS* (Voltages Referenced to V ) ASS
Symbol Parameter Value Unit
V DC Supply Voltage – 0.5 to + 18.0 VDD
BLOCK DIAGRAM
V , V Input or Output Voltage (DC or Transient) – 0.5 to V + 0.5 Vin out DD
6l , l Input or Output Current (DC or Transient), ± 10 mAin out
per Pin
S
5 D Q 1P Power Dissipation, per Package† 500 mWD
T Storage Temperature – 65 to + 150 Cstg
T Lead Temperature (8–Second Soldering) 260 C 3 C Q 2L
R
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: 4
Plastic P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
8Ceramic L” Packages: – 12 mW/ C From 100 C To 125 C
S
9 D Q 13
TRUTH TABLE
Inputs Outputs
† 11 C Q 12Clock Data Reset Set Q Q
R
0 0 0 0 1
10
1 0 0 1 0
V = PIN 14DDNo
X 0 0 Q Q V = PIN 7SSChange
X X 1 0 0 1
X X 0 1 1 0
X X 1 1 1 1
X = Don’t Care
† = Level Change
REV 3
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 Motorola, Inc. 1995MOTOROLA CMOS LOGIC DATA MC14013B
45