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Multicell Battery Stack Monitor

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Description

Niveau: Supérieur, Doctorat, Bac+8
LTC6802-1 1 68021fa TYPICAL APPLICATION DESCRIPTION Multicell Battery Stack Monitor The LTC®6802-1 is a complete battery monitoring IC that includes a 12-bit ADC, a precision voltage reference, a high voltage input multiplexer and a serial interface. Each LTC6802-1 can measure up to 12 series connected bat- tery cells with an input common mode voltage up to 60V. In addition, multiple LTC6802-1 devices can be placed in series to monitor the voltage of each cell in a long battery string. The unique level-shifting serial interface allows the serial ports of these devices to be daisy-chained without optocouplers or isolators. When multiple LTC6802-1 devices are connected in series they can operate simultaneously, permitting all cell voltages in the stack to be measured within 13ms. To minimize power, the LTC6802-1 offers a measure mode, which simply monitors each cell for overvoltage and un- dervoltage conditions. A standby mode is also provided. Each cell input has an associated MOSFET switch for discharging overcharged cells. For large battery stack applications requiring individually addressable serial communications, see the LTC6802-2. FEATURES APPLICATIONS n Measures up to 12 Li-Ion Cells in Series (60V Max) n Stackable Architecture Enables >1000V Systems n 0.25% Maximum Total Measurement Error n 13ms to Measure All Cells in a System n Cell Balancing: On-Chip Passive Cell Balancing Switches Provision for Off-Chip Passive Balancing n Two Thermistor Inputs Plus On-Board Temperature Sensor n 1MHz Daisy-Chainable Serial Interface n High

  • vreg vref

  • ?a ?a

  • pin sdi

  • pins csbo

  • mv mv

  • current high

  • voltage range

  • digital input

  • cell voltage


Subjects

Informations

Published by
Reads 90
Language English

LTC6802-1
Multicell
Battery Stack Monitor
FEATURES DESCRIPTION
®n Measures up to 12 Li-Ion Cells in Series (60V Max) The LTC 6802-1 is a complete battery monitoring IC that
n Stackable Architecture Enables >1000V Systems includes a 12-bit ADC, a precision voltage reference, a
n high voltage input multiplexer and a serial interface. Each 0.25% Maximum Total Measurement Error
n LTC6802-1 can measure up to 12 series connected bat- 13ms to Measure All Cells in a System
n tery cells with an input common mode voltage up to 60V. Cell Balancing:
In addition, multiple LTC6802-1 devices can be placed in On-Chip Passive Cell Balancing Switches
series to monitor the voltage of each cell in a long battery Provision for Off-Chip Passive Balancing
n string. The unique level-shifting serial interface allows the Two Thermistor Inputs Plus On-Board
serial ports of these devices to be daisy-chained without Temperature Sensor
n optocouplers or isolators. 1MHz Daisy-Chainable Serial Interface
n High EMI Immunity When multiple LTC6802-1 devices are connected in series
n Delta Sigma Converter with Built-In Noise Filter they can operate simultaneously, permitting all cell voltages
n Open Wire Connection Fault Detection in the stack to be measured within 13ms.
n Low Power Modes
To minimize power , the L TC6802-1 offers a measure mode, n 44-Lead SSOP Package
which simply monitors each cell for overvoltage and un-
dervoltage conditions. A standby mode is also provided.APPLICATIONS
Each cell input has an associated MOSFET switch for
n Electric and Hybrid Electric Vehicles
discharging overcharged cells.
n High Power Portable Equipment
n For large battery stack applications requiring individually Backup Battery Systems
n addressable serial communications, see the LTC6802-2. High Voltage Data Acquisition Systems
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
NEXT 12-CELL Measurement Error Over
SERIAL DATAPACK ABOVE LTC6802-1
+ Extended TemperatureTO LTC6802-1V
ABOVEDIE TEMP 0.30
0.25
7 REPRESENTATIVE
0.20REGISTERS UNITS
AND 0.15
CONTROL
0.10
12-CELL 0.05
MUXBATTERY
0STRING
–0.05
12-BIT
–0.10Δ∑ ADC
–0.15
–0.20
–0.25VOLTAGE
– SERIAL DATAV REFERENCE –0.30EXTERNAL TO LTC6802-1 –50 –25 0 25 50 75 100 125TEMPNEXT 12-CELL BELOW TEMPERATURE (°C)PACK BELOW 68021 TA01a
68021 TA01b
100k
100k NTC
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MEASUREMENT ERROR (%)LTC6802-1
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
(Note 1)
TOP VIEW+ –Total Supply Voltage (V to V ) .................................60V
CSBO 1 44 CSBI–Input Voltage (Relative to V )
SDOI 2 43 SDO
C1 ............................................................ –0.3V to 9V
SCKO 3 42 SDI+ +C12 .......................................... V – 0.6V to V + 0.3V +V 4 41 SCKI
Cn (Note 5) ......................... –0.3V to min (9 • n, 60V)
C12 5 40 VMODE
Sn (Note 5) –0in (9 • n, 60V) S12 6 39 GPIO2
+ +CSBO, SCKO, SDOI .................. V – 0.6V to V + 0.3V C11 7 38 GPIO1
All other pins ........................................... –0.3V to 7V S11 8 37 WDTB
Voltage Between Inputs C10 9 36 MMB
S10 10 35 TOSCn to Cn-1 ................................................ –0.3V to 9V
C9 11 34 VREGSn to Cn-1 –0
S9 12 33 VREFC12 to C8 ............................................... –0.3V to 25V
C8 13 32 VTEMP2C8 to C4 ................................................. –0V
– S8 14 31 VTEMP1C4 to V –0.3V to 25V
C7 15 30 NCOperating Temperature Range .................–40°C to 85°C
–S7 16 29 V
Specified Temperatur..................–40°C to 85°C
C6 17 28 S1
Junction Temperature ........................................... 150°C
S6 18 27 C1
Storage Temperature Range .................. –65°C to 150°C
C5 19 26 S2
S5 20 25 C2
*n = 1 to 12 C4 21 24 S3
S4 22 23 C3
G PACKAGE
44-LEAD PLASTIC SSOP
T = 150°C, θ = 70°C/WJMAX JA
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC6802IG-1#PBF LTC6802IG-1#TRPBF LTC6802G-1 44-Lead Plastic SSOP –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.TC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
+ –temperature range, otherwise specifications are at T = 25°C. V = 43.2V, V = 0V, unless otherwise noted.A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Specifications
V Measurement Resolution Quantization of the ADC l 1.5 mV/BitACC
lADC Offset Voltage (Note 2) –0.5 0.5 mV
ADC Gain Error (Note 2) –0.12 0.12 %
l –0.22 0.22 %
V Total Measurement Error (Note 4)ERR
V = 0V 0.8 mVCELL
V = 2.3V –2.8 2.8 mVCELL
V l –5.1 5.1 mVCELL
V = 3.6V –4.3 4.3 mVCELL
V l –7.9 7.9 mVCELL
V = 4.2V –5 5 mVCELL
V l –9.2 9.2 mVCELL
V = 4.6V ±8 mVCELL
V = 2.3V l –5.1 5.1 mVTEMP
V = 3.6V l –7.9 7.9 mVTEMP
V = 4.2V l –9.2 9.2 mVTEMP
V Cell Voltage Range Full Scale Voltage Range 5 VCELL
lV Common Mode Voltage Range Measured Range of Inputs CN for <0.25% Gain Error, N = 3 to 11 3.7 5 • N VCM
– lRelative to V Range of Input C3 for <1% Gain Error 1.8 15 V
lRange of Input C2 for <0.25% Gain Error 1.2 10 V
lRange of Input C1 for <0.25% Gain Error 0 5 V
Overvoltage (OV) Detection Level Programmed for 4.2V l 4.182 4.200 4.218 V
Undervoltage (UV) Detection Level Programmed for 2.3V l 2.290 2.300 2.310 V
Die Temperature Measurement Error Error in Measurement at 125°C 3 °C
–V Reference Pin Voltage R = 100k to V 3.020 3.065 3.110 VREF LOAD
l 3.015 3.065 3.115 V
Reference Voltage Temperature Coefficient 8 ppm/°Coltage Thermal Hysteresis 25°C to 85°C and 25°C to –40°C 100 ppm
Reference Voltage Long Term Drift 60 ppm/√khr
+ lV Regulator Pin Voltage 10 < V < 50, No Load 4.5 5.0 5.5 VREG
lI = 4mA 4.1 4.8 VLOAD
Regulator Pin Short Circuit Current Limit l 58 mA
+ –V Supply Voltage, V Relative to V V Specifications Met l 10 50 VS ERR
Timing Specifications Met l 4 50 V
I Input Bias Current In/Out of Pins C1 Thru C12B
lWhen Measuring Cells –10 10 μA
When Not Measuring Cells 1 nA
+I Supply Current, Active Current Into the V Pin when Measuring Voltages 0.8 1.1 mAS
lwith the ADC 1.2 mA
+I Supply Current, Monitor Mode Average Current Into the V Pin While Monitoring M
for UV and OV Conditions
Continuous Monitoring (CDC = 2) 800 μA
Monitor Every 130ms (CDC = 5) 225 μAy 500ms (CDC = 6) 150 μAy 2s (CDC = 7) 100 μA
+I Supply Current, Idle Current into the V Pin When Idle 35 60 80 μAQS
All Serial Port Pins at Logic ‘1’ l 30 85 μA
lI Supply Current, Serial I/O All Serial Port Pins at Logic ‘0’ V = 0, This 3 4.5 mACS MODE
Current is Added to I or IS QS
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ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
+ –temperature range, otherwise specifications are at T = 25°C. V = 43.2V, V = 0V, unless otherwise noted.A
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Discharge Switch On-Resistance V > 3V (Note 3) l 10 20 ΩCELL
lTemperature Range –40 85 °C
Thermal Shutdown Temperature 145 °C
Thermal Shutdown Hysteresis 5°C
Voltage Mode Timing Specifications
lt Measurement Cycle Time Time Required to Measure 11 or 12 Cells 11 13 16 msCYCLE
lTime Required to Measure Up to 10 Cells 9.2 11 13.5 ms
Time Required to Measure 1 Cell 1 1.2 1.5 ms
t SDI Valid to SCKI Rising Setup l 10 ns1
t SDI Valid to SCKI Rising Hold l 250 ns2
lt SCKI Low 400 ns3
lt SCKI High 400 ns4
t CSBI Pulse Width l 400 ns5
t SCKI Rising to CSBI Rising l 100 ns6
lt CSBI Falling to SCKI Rising 100 ns7
lt SCKI Falling to SDO Valid 250 ns8
Clock Frequency l 1 MHz
Watchdog Timer Time Out Period l 1 2.5 s
Timing Specifications
lt CSBI to CSBO C = 150pF 600 nsPD1 CSBO
t SCKI to SCKO C l 300 nsPD2 SCKO
t SDI to SDOI Write Delay C = 150pF l 300 nsPD3 SDOI
lt SDOI to SDI Read Delay C 300 nsPD4 SDO
Voltage Mode Digital I/O Specifications
V Digital Input Voltage High Pins SCKI, SDI, and CSBI l2VIH
Voltage Low l 0.8 VIL
lV Digital Output VPin SDO; Sinking 500μA 0.3 VOL
Current Mode Digital I/O Specifications
I Digital Input Current High Pins CSBI, SCKI, and SDI (Write) l 10 μAIH1
lI Digital Input Current Low 1000 μAIL1
lIPin SDOI (Read) –1000 μAIH2
I l –10 μAIL2
I Digital Output Current High Pins CSBO, SCKO, and SDOI (Write) l 310 μAOH1
lI Digital Output Current Low 1000 1200 1650 μAOL1
lIPin SDI (Read) –1650 –1200 –1000 μAOH2
I l –10 –3 0 μAOL2
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: Due to the contact resistance of the production tester, this
may cause permanent damage to the device. Exposure to any Absolute specification is tested to relaxed limits. The 20Ω limit is guaranteed by
Maximum Rating condition for extended periods may affect device design.
reliability and lifetime. Note 4: V refers to the voltage applied across the following pin CELL
–Note 2: The ADC specifications are guaranteed by the Total Measurement combinations: Cn to Cn-1 for n = 2 to 12, C1 to V . V refers to the TEMP
–Error (V ) specification. voltage applied from V or V to V .ERR TEMP1 TEMP2
Note 5: These absolute maximum ratings apply provided that the voltage
between inputs do not exceed their absolute maximum ratings.
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TYPICAL PERFORMANCE CHARACTERISTICS
Cell Measurement Total
Cell Measurement Total Unadjusted Error Measurement Gain Error
Unadjusted Error vs Input Resistance Hysteresis
10 10 25
T = 85°C TO 25°CT = –40°C AA
8 T = 25°C 0A
T = 85°CA6 20–10T = 125°CA
4
–20
2 15
–30
0
–40 R = 1kS 10–2
R = 2kS–50
R = 5k–4 S
R = 10kS–60–6 5
R IN SERIES WITH CN AND CN-1S
–70 NO EXTERNAL CAPACITANCE ON –8
CN AND CN-1
–10 –80 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –250–200–150–100 –50 0 50 100 150 200
CELL VOLTAGE (V) CHANGE IN GAIN ERROR (ppm)CELL VOLTAGE (V)
68021 G02 68021 G0368021 G01
Measurement Gain Error Cell Measurement Common Mode ADC Normal Mode Rejection
Hysteresis Rejection vs Frequency
20 0 0
T = –45°C TO 25°C V = 5VA CM(IN) P-P
18 72dB REJECTION
–10 –10CORRESPONDS TO
16 LESS THAN 1 BIT
–20 AT ADC OUTPUT –2014
12
–30 –30
10
–40 –40
8
6 –50 –50
4
–60 –60
2
0 –70 –70
–250–200–150–100 –50 0 50 100 150 200 10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k
CHANGE IN GAIN ERROR (ppm) FREQUENCY (Hz) FREQUENCY (Hz)
68021 G04 68021 G05 68021 G06
ADC INL ADC DNL Cell Input Bias Current in Standby
2.0 1.0 50
0.8
1.5
40
0.6
1.0
0.4
30
0.5 C10.2
0 0 20
C12–0.2
–0.5
10–0.4
–1.0
–0.6
0
–1.5 –0.8 C2 TO C11
–2.0 –1.0 –10
0 12 3 4 5 0 12 3 4 5 –40 –20 0 20 40 60 80 100 120
INPUT (V) INPUT (V) TEMPERATURE (°C)
68021 G07 68021 G08 68021 G09
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INL (BITS)
TOTAL UNADJUSTED ERROR (mV)
NUMBER OF UNITS
DNL (BITS)
TOTAL UNADJUSTED ERROR (mV)
REJECTION (db)
REJECTION (db)
C PIN BIAS CURRENT (nA)
NUMBER OF UNITSLTC6802-1
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current Supply Current Cell Input Bias Current During
vs Supply Voltage Standby vs Supply Voltage in CDC = 2Conversion
60 0.902.70
CELL INPUT = 3.6V CDC = 2 (CONTINUOUS
CELL CONVERSIONS)
2.65 50 0.85
T = 85°CA
2.60 T = 85°CA
40 0.80
T = –40°C2.55 A
T = 25°CA30 0.75
2.50 T = –40°CA
20 0.70
2.45 T = 25°CA
10 0.65
2.40
0 0.602.35
–40 –20 0 20 40 60 80 100 120 0 10 20 30 40 50 60 0 10 20 30 40 50 60
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)TEMPERATURE (°C)
68021 G11 68021 G1268021 G10
Internal Die Temperature External Temperature
Measurement Measurement Total Unadjusted V Output Voltage REF
vs Ambient Temperature Error vs Input vs Temperature
5 3.07010
V = 43.2VS T = –40°CA
4 T = 25°CA 3.068
5 T = 85°CA3
T = 105°CA
3.0662
0
1
3.064
0 –5
3.062
–1
–10
–2 3.060
–3
DEVICE IN STANDBY PRIOR TO –15 3.058
–4 MAKING DIE MEASUREMENTS
TO MINIMIZE SELF-HEATING 5 REPRESENTATIVE UNITS
–5 3.056–20
–50 –25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 –50 –25 0 25 50 75 100 125
AMBIENT TEMPERATURE (°C) TEMPERATURE (°C)TEMPERATURE INPUT VOLTAGE (V)
68021 G13 68021 G1568021 G14
V Load Regulation V Line Regulation V Load RegulationREF REF REG
3.09 3.074 5.4
NO EXTERNAL LOAD ON V , CDC = 2 REF
(CONTINUOUS CELL CONVERSIONS)
3.072 5.2
3.08
T = 85°CA3.070 5.0
T = 25°CA3.07
3.068 4.8T = 85°CA T = 25°CA
T = 85°CT = 25°C AA T = –40°CA3.066 4.63.06
T = –40°CA
T = –40°C 3.064 4.4A
3.05
3.062 4.2
3.04 3.060 4.0
0 10 100 1000 0 10 20 30 40 50 60 013524 6789 10
SOURCING CURRENT (μA) SUPPLY VOLTAGE (V) SUPPLY CURRENT (mA)
68021 G16 68021 G17 68021 G18
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DIFFERENCE BETWEEN INTERNAL DIE TEMPERATURE
V (V)
C PIN BIAS CURRENT (μA)
REF
MEASUREMENT AND AMBIENT TEMPERATURE (°C)
V (V)
REF
TOTAL UNADJUSTED ERROR (mV)
STANDBY SUPPLY CURRENT (μA)
V (V)
REF
V (V) SUPPLY CURRENT (mA)
REGLTC6802-1
TYPICAL PERFORMANCE CHARACTERISTICS
Internal Discharge Resistance
V Line Regulation vs Cell VoltageREG
5.5 50
T = –45°CA
45 T = 25°CAT = 85°CA T = 85°CA5.0 40 T = 105°CA
35
T = –40°CA4.5 30
T = 25°CA 25
4.0 20
15
3.5 10
NO EXTERNAL LOAD ON V , CDC = 2 5REG
(CONTINUOUS CELL CONVERSIONS)
3.0 0
5 15 25 35 45 55 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SUPPLY VOLTAGE (V) CELL VOLTAGE (V)
68021 G19 68021 G20
Die Temperature Increase vs
Discharge Current in Internal FET Cell Conversion Time
50 13.20
ALL 12 CELLS AT 3.6V
45 V = 43.2VS 13.15
T = 25°CA
40
13.10
35
13.0530
12 CELLS
DISCHARGING25 13.00
6 CELLS
DISCHARGING20
12.95
15 1 CELL 12.90
DISCHARGING10
12.855
0 12.80
0 10 20 30 40 50 60 70 80 –40 –20 0 20 40 60 80 100 120
DISCHARGE CURRENT PER CELL (mA) TEMPERATURE (°C)
68021 G21 68021 G22
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V (V)
REG
INCREASE IN DIE TEMPERATURE (°C)
CONVERSION TIME (ms)
DISCHARGE RESISTANCE (Ω)LTC6802-1
PIN FUNCTIONS
– –CSBO (Pin 1): Chip Select Output (Active Low). CSBO is V (Pin 29): Connect V to the most negative potential in
a buffered version of the chip select input, CSBI. CSBO the series of cells.
drives the next IC in the daisy chain. See Serial Port in the –NC (Pin 30): Pin 30 is internally connected to V through
Applications Information section. 10Ω. Pin 30 can be left unconnected or connected to pin
SDOI (Pin 2): Serial Data I/O Pin. SDOI transfers data to 29 on the PCB.
and from the next IC in the daisy chain. See Serial Port in V , V (Pins 31, 32): Temperature Sensor Inputs. TEMP1 TEMP2the Applications Information section. The ADC measures the voltage on V with respect to TEMPx
–SCKO (Pin 3): Serial Clock Output. SCKO is a buffered ver- V and stores the result in the TMP registers. The ADC
sion of SCKI. SCKO drives the next IC in the daisy chain. measurements are relative to the V pin voltage. Therefore REF
See Serial Port in the Applications Information section. a simple thermistor and resistor combination connected
to the V pin can be used to monitor temperature. The + REFV (Pin 4): Tie pin 4 to the most positive potential in the
V inputs can also be general purpose ADC inputs.+ TEMPbattery stack. Typically V is the same potential as C12.
V (Pin 33): 3.075V Voltage Reference Output. This pin REFC12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1 (Pins
should be bypassed with a 1μF capacitor. The V pin can REF5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27): C1 through –drive a 100k resistive load connected to V . Larger loads C12 are the inputs for monitoring battery cell voltages.
should be buffered with an LT6003 op amp, or similar Up to 12 cells can be monitored. The lowest potential is
device.–tied to pin V . The next lowest potential is tied to C1 and
so forth. See the figures in the Applications Information V (Pin 34): Linear Voltage Regulator Output. This pin REG
section for more details on connecting batteries to the should be bypassed with a 1μF capacitor. The V pin is REG
LTC6802-1. capable of supplying up to 4mA to an external load. The
V pin does not sink current.REGThe LTC6802-1 can monitor a series connection of up
to 12 cells. Each cell in a series connection must have TOS (Pin 35): Top of Stack Input. Tie TOS to V when REG
a common mode voltage that is greater than or equal to the LTC6802-1 is the top device in a daisy chain. Tie TOS
–the cells below it. to V when the LTC6802-1 is any other device in a daisy
chain. When TOS is tied to V , the LTC6802-1 ignores REGS12, S11, S10, S9, S8, S7, S6, S5, S4, S3, S2, S1 (Pins –the SDOI input. When TOS is tied to V , the LTC6802-1 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28): S1 though
expects data to be passed to and from the SDOI pin.S12 pins are used to balance battery cells. If one cell in a
series becomes over charged, an S output can be used to MMB (Pin 36): Monitor Mode (Active Low) Input. When
–discharge the cell. Each S output has an internal N-channel MMB is low (same potential as V ), the LTC6802-1 goes
MOSFET for discharging. See the Block Diagram. The NMOS into monitor mode. See Modes of Operation in the Ap-
has a maximum on resistance of 20Ω. An external resistor plications Information section.
should be connected in series with the NMOS to dissipate WDTB (Pin 37): Watchdog Timer Output (Active Low). If
heat outside of the LTC6802-1 package. When using the there is no activity on the SCKI pin for 2.5 seconds, the
internal MOSFETs to discharge cells, the die temperature WDTB output is asserted. The WDTB pin is an open drain
should be monitored. See Power Dissipation and Thermal NMOS output. When asserted it pulls the output down
Shutdown in the Applications Information section. –to V and resets the configuration register to its default
The S pins also feature an internal 10k pull-up resistor . This state. See Watchdog Timer Circuit in the Applications
allows the S pins to be used to drive the gates of external Information section.
P-channel MOSFETs for higher discharge capability.
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8LTC6802-1
PIN FUNCTIONS
GPIO1, GPIO2 (Pins 38, 39): General Purpose Input/Out- standard TTL logic levels. Connect V to V when MODE REG
put. The operation of these pins depends on the state of the LTC6802-1 is the bottom device in a daisy chain.
the MMB pin. –When V is connected to V , the SCKI, SDI, and CSBI MODE
When MMB is high, the pins behave as traditional GPIOs. pins are configured as current inputs and outputs, and SDO
–By writing a “0” to a GPIO configuration register bit, the is unused. Connect V to V when the LTC6802-1 is MODE
–open drain output is activated and the pin is pulled to V . being driven by another LTC6802-1 in a daisy chain.
By writing a logic “1” to the configuration register bit, the SCKI (Pin 41): Serial Clock Input. The SCKI pin interfaces
corresponding GPIO pin is high impedance. An external to any logic gate (TTL levels) if V is tied to V . SCKI MODE REGresistor is needed to pull the pin up to V .REG must be driven by the SCKO pin of another LTC6802-1 if
–By reading the configuration register locations GPIO1 V is tied to V . See Serial Port in the Applications MODE
and GPIO2, the state of the pins can be determined. For Information section.
example, if a “0” is written to register bit GPIO1, a “0” is SDI (Pin 42): Serial Data Input. The SDI pin interfaces to
always read back because the output NMOSFET pulls pin any logic gate (TTL levels) if V is tied to V . SDI MODE REG–38 to V . If a “1” is written to register bit GPIO1, the pin must be driven by the SDOI pin of another LTC6802-1 if
becomes high impedance. Either a “1” or a “0” is read –V is tied to VMODEback, depending on the voltage present at pin 38. The Information section.
GPIOs makes it possible to turn on/off circuitry around
SDO (Pin 43): Serial Data Output. The SDO pin is an NMOS the LTC6802-1, or read logic values from a circuit around
open drain output if V is tied to V . SDO is not used the LTC6802-1. MODE REG
–if V is tied to V . See Serial Port in the Applications MODEWhen the MMB pin is low, the GPIO pins and the WDTB Information section.
pin are treated as inputs that set the number of cells to
CSBI (Pin 44): Chip Select (Active Low) Input. The CSBI be monitored. See Monitor Mode in the Applications
pin interfaces to any logic gate (TTL levels) if V is tied Information section. MODE
to V . CSBI must be driven by the CSBO pin of another REGV (Pin 40): Voltage Mode Input. When V is tied to –MODE MODE LTC6802-1 if V is tied to V . See Serial Port in the MODEV , the SCKI, SDI, SDO, and CSBI pins are configured as REG Applications Information section.
voltage inputs and outputs. This means these pins accept
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9LTC6802-1
BLOCK DIAGRAM
4
+V
5 REGULATOR 34C12 VREG
10k
6
S12 WATCHDOG
37
TIMER WDTB
7
C11
3
SCKO
2
SDOI
10k
1
CSBO
24
12 RESULTS S3
Δ∑ A/D CONVERTER REGISTERMUX
AND 44
CSBICOMMUNICATIONS25
C2 43
SDO
10k
42
SDI
26
S2 41
SCKI
27
C1 40REFERENCE VMODE
10k
39
GPIO2
28
S1 CONTROL 38
GPIO1
36
MMB29 –V
35
10Ω TOS
30 EXTERNALDIENC
TEMPTEMP
V V VTEMP1 TEMP2 REF
31 32 33 68021 BD
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