HEXFET® Power MOSFET IRFI540N

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Description

Niveau: Secondaire, Lycée, Terminale
HEXFET® Power MOSFET IRFI540N PD - 9.1361A 3/16/98 VDSS = 100V RDS(on) = 0.052? ID = 20AS D G TO-220 FULLPAK l Advanced Process Technology l Isolated Package l High Voltage Isolation = 2.5KVRMS ? l Sink to Lead Creepage Dist. = 4.8mm l Fully Avalanche Rated Parameter Min. Typ. Max. Units R?JC Junction-to-Case –––– –––– 2.8 R?JA Junction-to-Ambient –––– –––– 65 Thermal Resistance Parameter Max. Units ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 20 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 14 A IDM Pulsed Drain Current ?? 110 PD @TC = 25°C Power Dissipation 54 W Linear Derating Factor 0.36 W/°C VGS Gate-to-Source Voltage ±20 V EAS Single Pulse Avalanche Energy ?? 300 mJ IAR Avalanche Current?? 16 A EAR Repetitive Avalanche Current? 5.4 mJ dv/dt Peak Diode Recovery dv/dt ?? 5.0 V/ns TJ Operating Junction and -55 to + 175 TSTG Storage Temperature Range °C Soldering Temperature, for 10 seconds 300 (1.6mm from case) Mounting torque, 6-32 or M3 screw. 10 lbf•in (1.1N•m) Absolute Maximum Ratings Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area.

  • tj ≤

  • junction tem

  • body diode

  • junction temperature

  • operating area

  • typical output

  • temperature range °c

  • µs


Subjects

Informations

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PRELIMINARY
HEXFET
®
Power MOSFET
l
Advanced Process Technology
l
Isolated Package
l
High Voltage Isolation = 2.5KVRMS
U
l
Sink to Lead Creepage Dist. = 4.8mm
l
Fully Avalanche Rated
G
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
device for use in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial applications.
The moulding compound used provides a high isolation
capability and a low thermal resistance between the tab
and external heatsink. This isolation is equivalent to using
a 100 micron mica barrier with standard TO-220 product.
The Fullpak is mounted to a heatsink using a single clip or
by a single screw fixing.
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°CContinuous Drain Current, V
GS
@ 10V
I
D
@ T
C
= 100°CContinuous Drain Current, V
GS
@ 10V
I
DM
Pulsed Drain Current
QV
P
D
@T
C
= 25°CPower Dissipation
Linear Derating Factor
V
GS
Gate-to-Source Voltage
E
AS
Single Pulse Avalanche Energy
I
AR
Avalanche Current
QV
E
AR
Repetitive Avalanche Current
Q
dv/dtPeak Diode Recovery dv/dt
SV
T
J
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw.
Thermal Resistance
Parameter
R
q
JC
Junction-to-Case
R
q
JA
Junction-to-Ambient

VRPD - 9.1361A
IRFI540N
DV
DSS
= 100V
R
DS(on)
= 0.052
W
S
I
D
= 20A

TO-220 FULLPAK

Max.Units
02A41011W450.36W/°C
V02±Jm003A61Jm4.55.0V/ns
-55 to + 175
C°300 (1.6mm from case)
10 lbfin (1.1Nm)
Min.Typ.Max.Units
2.8
65°C/W
3/16/98

VVTIRFI540N
Electrical Characteristics @ T
J
= 25°C (unless otherwise specified)
ParameterMin.Typ.Max.Units

Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage100V
GS
V = 0V, I
D
= 250µA
D
V
(BR)DSS
/
D
T
J
Breakdown Voltage Temp. Coefficient0.11V/°CReference to 25°C
D
,

I= 1mA
R
DS(on)
Static Drain-to-Source On-Resistance0.052
W
V
GS
= 10V, I
D
= 11A
T
V
GS(th)
Gate Threshold Voltage2.04.0V
D
V
S
= V
GS
, I
D
= 250µA
g
fs
Forward Transconductance11S
DS
V = 50V, I
D
= 16A
V
25
DS
V = 100V, V
GS
= 0V
I
DSS
Drain-to-Source Leakage Current250µA
DS
V = 80V, V
GS
= 0V, T
J
= 150°C
Gate-to-Source Forward Leakage100
GS
V = 20V
I
GSS
Gate-to-Source Reverse Leakage-100nA
GS
V = -20V
Q
g
Total Gate Charge94
D
I= 16A
Q
gs
Gate-to-Source Charge15nC
DS
V = 80V
Q
gd
Gate-to-Drain ("Miller") Charge43
GS
V = 10V, See Fig. 6 and 13
t
d(on)
Turn-On Delay Time8.2
DD
V = 50V
t
r
Rise Time39
D
I= 16A
t
d(off)
Turn-Off Delay Time44ns
G
R= 5.1
W
t
f
Fall Time33
D
R= 3.0
W∃
See Fig. 10
TV
L
D
Internal Drain Inductance4.5Between lead,
6mm (0.25in.)
nHfrom package
G
L
S
Internal Source Inductance


7.5


and center of die contact
C
iss
Input Capacitance1400
GS
V = 0V
C
oss
Output Capacitance330pF
DS
V = 25V
C
rss
Reverse Transfer Capacitance170 = 1.0MHz, See Fig.
V
5
CDrain to Sink Capacitance12 = 1.0MHz
Source-Drain Ratings and Characteristics
ParameterMin.Typ.Max.Units

Conditions
I
S
Continuous Source Current20MOSFET symbol
(Body Diode)Ashowing the
I
SM
Pulsed Source Current110integral reverse
G
(Body Diode)
QV
p-n junction diode.
V
SD
Diode Forward Voltage1.3V
J
T= 25°C, I
S
= 11A, V
GS
= 0V
t
rr
Reverse Recovery Time170250ns
J
T = 25°C, I
F
= 16A
Q
rr
Reverse RecoveryCharge1.11.6µCdi/dt = 100A/µ

s
T
Notes:
Q
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )

R
VR
DGD
== 2255
W
V,, Is
A
t
S
a

r=t in1g6 AT.
J


(=S e2e5 °FCig, uLr e= 122.)0mH
S
I
SD
£
16A, di/dt
£
210A/µs, V
DD
£
V
(BR)DSS
,
T
J
£
175°C

VT
Pulse width
£
300µs; duty cycle
£
2%.
U
t=60s, =60Hz
Uses IRF540N data and test conditions

VTDS

DS

0001 VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
001

01

V5.4

T2 0
C
µ=s 2P5U°LCSE WIDTH
1A0.1110100
V
D

S
, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics

0001

001T
J
= 25°C
T
J
= 175°C
01 2V0
D
µ
S
s= P5U0LVSE WIDTH
145678910
A
V
G

S
, Gate-to-Source Voltage (V)
Fig 3.
Typical Transfer Characteristics

0001 VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
001

IRFI540N

10
4.5V

2T 0
C
µ=s 1P7U5L°SCE WIDTH
1A0.1110100
V
D

S
, Drain-to-Source Voltage (V)
Fig 2.
Typical Output Characteristics

3.0
I
D
= 27A
5.20.25.10.15.00.0
V
G

S
= 10V
-60-40-20020406080100120140160180
A
T
J
, Junction Temperature (°C)
Fig 4.
Normalized On-Resistance
Vs. Temperature

IRFI540N

0042V = 0V, f = 1MHz
SGC =C +C ,C SHORTED
iss




gs




gd



ds
C = C
rss


gd
0002 CC =C + C
ssioss



ds


gd
00610021 Csso008 Cssr0040A110100
V , Drain-to-Source Voltage (V)
SDFig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage

1000

001T
J
= 175°C
T
J
= 25°C
10
V
G

S
= 0V
A
0.40.81.21.62.0
V
S

D
, Source-to-Drain Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage

02I
D
= 16A V
D

S
= 80V
V
D

S
= 50V
16
V
D

S
= 20V
2184 F OSRE ET EFISGTU CRIER C13UIT
0A020406080100
Q
G
, Total Gate Charge (nC)
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage

0001 OPERATION IN THIS AREA LIMITED
BY R
DS(on)

001sµ01sµ00101sm1 T
C
= 25°C
T
J
= 175°C
10ms
1
Single Pulse
A
1101001000
V
D

S
, Drain-to-Source Voltage (V)
Fig 8.
Maximum Safe Operating Area

02510150255075100125150175
T
C
, Case Temperature( ° C)
Fig 9.
Maximum Drain Current Vs.
Case Temperature
01

IRFI540N
RDVSDV
GS
D.U.T.
R
G
-
+
V
DD
V01DPuutlsy eF aWcitdotrh
££ 01& 1
µ
%
s
Fig 10a.
Switching Time Test Circuit
VSD%09%01VSGt
d(on)
t
r
t
d(off)
t
f
Fig 10b.
Switching Time Waveforms

D = 0.50
1 .00201.00.05P
DM
0.10.02t
1
10.0SINGLE PULSEt
2
(THERMAL RESPONSE)Notes:
1. Duty factor D =t
1
/ t
2
2. Peak T
J
=P
DM
x Z
thJC
+ T
C
10.00.000010.00010.0010.010.1 1 10
t
1
, Rectangular Pulse Duration (sec)

Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case

IRFI540N

LVSDD.U.T.
R+GVDD-10 V
I
AS
t
p
0.01
W
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
tpVDD

VSD

ISAFig 12b.
Unclamped Inductive Waveforms

QGV 01Q
GS
Q
GD
VGCharge
Fig 13a.
Basic Gate Charge Waveform

I
DTOP 6.6A
11A
BOTTOM 16A

0070060050040030020010
V
D

D
= 25V
A
255075100125150175
Starting T
J
, Junction Temperature (°C)

Fig 12c.
Maximum Avalanche Energy
Vs. Drain Current
CurrentRegulator
SameTypeasD.U.T.
WK0512V.2
m
F
Fm3.+D.U.T.-V
DS
VSGAm3IIGDCurrentSamplingResistors
Fig 13b.
Gate Charge Test Circuit

Q+

R-

T.U.D

RG

IRFI540N
Peak Diode Recovery dv/dt Test Circuit

+
Circuit Layout Considerations
·
Low Stray Inductance

·
Ground Plane

·
Low Leakage Inductance
Current Transformer

S-

T-+

·
dv/dt controlled by R
G
+
··
IDri vceor nstraolmlee dt ybpye Daust yD .FUa.cTt.or "D"
-
V
DD
DS·
D.U.T. - Device Under Test

Driver Gate DriveP.W.
P.W.PeriodD = Period

D.U.T. I
SD
Waveform
Reverse
CRuercroevnetryBody DCiourdree ntForward
td/idD.U.T. V
DS
WaveformDiode Recovery
td/vdRe-Applied
VoltageBody Diode Forward Drop
Inductor Curent
Ripple
£
5%
*
V
GS
= 5V for Logic Level Devices
Fig 14.
For N-Channel HEXFETS

V
GS
=10V
*

VDD

IDS

IRFI540N
Package Outline
TO-220 FullPak Outline
Dimensions are shown in millimeters (inches)
10.60 (.417)
10.40 (.409)ø33..1400 ((..112333))44..6800 ((..118819))
- A -3.70 (.145)
3.20 (.126)7.10 (.280)
6.70 (.263)
16.00 (.630)
15.80 (.622)1.15 (.045)
MIN.
1 2 3
33..1300 ((..112320))
- B -1133..5700 ((..553400))

22..6800 ((..110120))
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
NOTES:
1 DPIEMRE ANNSISOI NYI1N4.G5 M&, T1O98L2ERANCING
2 CONTROLLING DIMENSION: INCH.

CDAB3X00..4448 ((..001197))
2.85 (.112)
2.65 (.104)DMIISNTIMANUCM EC BREETEWPAEGENE
A-B-C-D = 4.80 (.189)

3X1.40 (.055)3X00..7900 ((..002385))
1.05 (.042)0.25 (.010)MA M B
2 . 5 42 (X.100)
Part Marking Information
TO-220 FullPak
EXAMPLE : THIS IS AN IRFI840G
WITH ASSEMBLY
A
LOT CODE E401INTERNATIONALPART NUMBER
RECTIFIERIRFI840G
LOGO
E401 9245
ASSEMBLYDATE CODE
LOT CODE(YYWW)
YY = YEAR
WW = WEEK

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http://www.irf.com/Data and specifications subject to change without notice.3/98

Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/