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IRLR U120N HEXFET® Power MOSFET

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Description

Niveau: Secondaire, Lycée, Terminale
IRLR/U120N HEXFET® Power MOSFET S D G VDSS = 100V RDS(on) = 0.185? ID = 10ADescription 5/11/98 Parameter Max. Units ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 10 ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 7.0 A IDM Pulsed Drain Current ?? 35 PD @TC = 25°C Power Dissipation 48 W Linear Derating Factor 0.32 W/°C VGS Gate-to-Source Voltage ± 16 V EAS Single Pulse Avalanche Energy?? 85 mJ IAR Avalanche Current?? 6.0 A EAR Repetitive Avalanche Energy?? 4.8 mJ dv/dt Peak Diode Recovery dv/dt ? 5.0 V/ns TJ Operating Junction and -55 to + 175 TSTG Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C Absolute Maximum Ratings Parameter Typ. Max. Units R?JC Junction-to-Case ––– 3.1 R?JA Junction-to-Ambient (PCB mount) ** ––– 50 °C/W R?JA Junction-to-Ambient ––– 110 Thermal Resistance D -P A K T O -252A A I-P A K T O -251AA l Surface Mount (IRLR120N) l Straight Lead (IRLU120N) l Advanced Process Technology l Fast Switching l Fully Avalanche Rated Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area.

  • power dissipation

  • tj ≤

  • source current

  • drain current

  • fully avalanche

  • diode forward

  • typical output

  • µs


Subjects

Informations

Published by
Reads 29
Language English

lllllSurface Mount (IRLR120N)
Straight Lead (IRLU120N)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient device for use in a wide
variety of applications.
The D-PAK is designed for surface mounting using
vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for through-
hole mounting applications. Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
Absolute Maximum Ratings
Parameter
I
D
@ T
C
= 25°CContinuous Drain Current, V
GS
@ 10V
I
D
@ T
C
= 100°CContinuous Drain Current, V
GS
@ 10V
I
DM
Pulsed Drain Current
QV
P
D
@T
C
= 25°CPower Dissipation
Linear Derating Factor
V
GS
Gate-to-Source Voltage
E
AS
Single Pulse Avalanche Energy
RV
I
AR
Avalanche Current
QV
E
AR
Repetitive Avalanche Energy
QV
dv/dtPeak Diode Recovery dv/dt
S
T
J
Operating Junction and
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Thermal Resistance
Parameter
R
q
JC
Junction-to-Case
R
q
JA
Junction-to-Ambient (PCB mount) **
R
q
JA
Junction-to-Ambient
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G

PD - 91541B
IRLR/U120N
HEXFET
®
Power MOSFET
DV
DSS
= 100V
R
DS(on)
= 0.185
W
S
I
D
= 10A

T OD--2P5A2KAA T OI--P2A51KAA

.xaM010.75384 0±. 3126
580.68.40.5-55 to + 175
300 (1.6mm from case )

Typ.Max.
3.1
05110

stinUAWC°/WVJmAJm/VsnC°

tinUsW/C°1

5/11/98

IRLR/U120N

VTElectrical Characteristics @ T
J
= 25°C (unless otherwise specified)
ParameterMin.Typ.Max.Units

Conditions
V
(BR)DSS
Drain-to-Source Breakdown Voltage100V
GS
V = 0V, I
D
= 250µA
D
V
(BR)DSS
/
D
T
J
Breakdown Voltage Temp. Coefficient0.12V/°CReference to 25°C, I
D
= 1mA
0.185
GS
V = 10V, I
D
= 6.0A
T
R
DS(on)
Static Drain-to-Source On-Resistance0.225W
GS
V = 5.0V, I
D
= 6.0A
T
0.265
GS
V = 4.0V, I
D
= 5.0A
T
V
GS(th)
Gate Threshold Voltage1.02.0V
D
V
S
= V
GS
, I
D
= 250µA
g
fs
Forward Transconductance3.1S
DS
V = 25V, I
D
= 6.0A
V
25V
DS
= 100V, V
GS
= 0V
I
DSS
Drain-to-Source Leakage Current250µA
DS
V = 80V, V
GS
= 0V, T
J
= 150°C
Gate-to-Source Forward Leakage100V
GS
= 16V
I
GSS
Gate-to-Source Reverse Leakage-100nA
GS
V = -16V
Q
g
Total Gate Charge20
D
I= 6.0A
Q
gs
Gate-to-Source Charge4.6nC
DS
V = 80V
Q
gd
Gate-to-Drain ("Miller") Charge10
GS
V = 5.0V, See Fig. 6 and 13
t
d(on)
Turn-On Delay Time4.0
DD
V = 50V
t
r
Rise Time35nsI
D
= 6.0A
t
d(off)
Turn-Off Delay Time23
G
R= 11
W∃
V
GS
= 5.0V
t
f
Fall Time22
D
R= 8.2
W∃
See Fig. 10
TV
Between lead,
D
L
D
Internal Drain Inductance 4.5 nH6mm (0.25in.)
from package
G
L
S
Internal Source Inductance 7.5and center of die contact
U
S
C
iss
Input Capacitance440
GS
V = 0V
C
oss
Output Capacitance97pF
DS
V = 25V
C
rss
Reverse Transfer Capacitance50 = 1.0MHz, See Fig.
V
5
Source-Drain Ratings and Characteristics
ParameterMin.Typ.Max.Units

Conditions
I
S
Continuous Source Current10MOSFET symbol
D
(Body Diode)Ashowing the
I
SM
Pulsed Source Currentintegral reverse
G
(Body Diode)
QV
35p-n junction diode.
S
V
SD
Diode Forward Voltage1.3V
J
T= 25°C, I
S
= 6.0A, V
GS
= 0V
T
t
rr
Reverse Recovery Time110160ns
J
T = 25°C, I
F
=6.0A
Q
rr
Reverse RecoveryCharge410620nCdi/dt = 100A/µ

s
TV
t
on
Forward Turn-On TimeIntrinsic turn-on time is negligible (turn-on is dominated by L
S
+L
D
)
Notes:
Q
Repetitive rating; pulse width limited by
T
Pulse width
£
300µs; duty cycle
£
2%.
max. junction temperature. ( See fig. 11 )
R
V
DD
= 25V, starting T
J
= 25°C, L = 4.7mH
U
This is applied for I-PAK, L
S
of D-PAK is measured between lead and
R
G
= 25
W
, I
AS
= 6.0A. (See Figure 12) center of die contact
S
I
SD
£
6.0A, di/dt
£
340A/µs, V
DD
£
V
(BR)DSS
,
V
Uses IRL520N data and test conditions.
T
J
£
175°C
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
2www.irf.com

nad001 VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
01

1

V5.2

T2
J
0 µ=s 2P5U°CLSE WIDTH
0.10.1110100
A
V
D

S
, Drain-to-Source Voltage (V)
Fig 1.
Typical Output Characteristics

001T
J
= 25°C
10
T
J
= 175°C

1 V
D

S
= 50V
0.1
20µs PULSE WIDTH
A
246810
V
G

S
, Gate-to-Source Voltage (V)
Fig 3.
Typical Transfer Characteristics
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001 VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
01

1

IRLR/U120N

V5.2

T2 0 µ=s 1P7U5°LCSE WIDTH
J0.10.1110100
A
V
D

S
, Drain-to-Source Voltage (V)
Fig 2.
Typical Output Characteristics

3.0
I
D
= 10A
5.20.25.10.15.00.0
V
G

S
= 10V
-60-40-20020406080100120140160180
A
T
J
, Junction Temperature (°C)
Fig 4.
Normalized On-Resistance
Vs. Temperature
3

IRLR/U120N

4

008V = 0V, f = 1MHz
SGC =C +C ,C SHORTED
iss




gs




gd





ds
C =C
rss




gd
C =C + C
oss



ds


gd
006 Cssi004 Csso002 Cssr0A110100
V , Drain-to-Source Voltage (V)
SDFig 5.
Typical Capacitance Vs.
Drain-to-Source Voltage

001

T
J
= 175°C
01T
J
= 25°C
1

V
G

S
= 0V
0.10.40.60.81.01.21.4
A
V
S

D
, Source-to-Drain Voltage (V)
Fig 7.
Typical Source-Drain Diode
Forward Voltage

V = 80V
SD V = 50V
SD V = 20V
SD

15
I
D
= 6.0A
21963 FOR TEST CIRCUIT
0
SEE FIGURE 13
A
0510152025
Q
G
, Total Gate Charge (nC)
Fig 6.
Typical Gate Charge Vs.
Gate-to-Source Voltage

001

011

OPERATION IN THIS AREA LIMITED
BY R
DS(on)
sµ01sµ001sm1sm01 TT
C
== 2157°5C°C
J0.1
Single Pulse
A
1101001000
V
D

S
, Drain-to-Source Voltage (V)
Fig 8.
Maximum Safe Operating Area
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018642A0255075100125150175
T
C
, Case Temperature (°C)
Fig 9.
Maximum Drain Current Vs.
Case Temperature

01

D = 0.50
10.20
01.050.020.00.10.01

(THSEIRNMGALLE RPEUSLPSOENSE)

IRLR/U120N

RDVSDV
GS
D.U.T.
RG+V-DDV0.5PDuultsye FWacitdotrh
££ 01& 1
µ
%
s
Fig 10a.
Switching Time Test Circuit
VSD%09%01VSGt
d(on)
t
r
t
d(off)
t
f
Fig 10b.
Switching Time Waveforms

PMDt1t2Notes:
21.. PDeutayk fTa
J
ct=orP D
D

M
=xt
1
Z/
t
t
hJ2C
+ T
C
0.00.1000010.00010.0010.010.1
t
1
, Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRLR/U120N

V51VDSLDRIVER
R
G
D.U.T+
IAS-V
DD
A
V01t
p
0.01
W
Fig 12a.
Unclamped Inductive Test Circuit
V
(BR)DSS
tp

ISAFig 12b.
Unclamped Inductive Waveforms
QGV 0.5Q
GS
Q
GD
VGCharge
Fig 13a.
Basic Gate Charge Waveform
6

I
DTOP 2.4A
4.2A
BOTTOM 6.0A

00206102108040A255075100125150175
Starting T
J
, Junction Temperature (°C)
Fig 12c.
Maximum Avalanche Energy
Vs. Drain Current

CurrentRegulator
SameTypeasD.U.T.
WK0512V.2
m
F.3
m
F
+D.U.T.-V
DS
VSGAm3IIGDCurrentSamplingResistors
Fig 13b.
Gate Charge Test Circuit
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QT7

IRLR/U120N

Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
·
Low Stray Inductance

·
Ground Plane
S

·
Low Leakage Inductance
Current Transformer
-

T.U.D

-+

+R-

·
dv/dt controlled by R
G
+
··
IDri vceor nstraomllee dt ybpye Daust yD .FUa.cTt.or "D"
-
V
DD
DS·
D.U.T. - Device Under Test

RG

V
GS
=10V
*

Driver Gate DriveP.W.
P.W.PeriodD = Period

D.U.T. I
SD
Waveform
Reverse
RecoveryBody Diode Forward
CurrentCurrentdi/dt
D.U.T. V
DS
WaveformDiode Recovery
dv/dtV
DDRe-Applied
VoltageBody Diode Forward Drop
Inductor Curent
Ripple
£
5%I
SD
*
V
GS
= 5V for Logic Level Devices
Fig 14.
For N-Channel HEXFETS

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IRLR/U120N

Package Outline
TO-252AA Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
6.73 (.265)2.19 (.086)1.14 (.045)
6.35 (.250)0.89 (.035)
- A -5.46 (.215)1.27 (.050)0.58 (.023)
5.21 (.205)0.88 (.035)0.46 (.018)
46.45 (.245)
6.22 (.245)5.68 (.224)
5.97 (.235)10.42 (.410)
1.02 (.040) 9.40 (.370)LEAD ASSIGNMENTS
1.64 (.025)1 2 3 1 - GATE
0.51 (.020) 2 - DRAIN
- B - MIN. 3 - SOURCE
1.52 (.060) 4 - DRAIN
1.15 (.045)0.89 (.035)
3X0.64 (.025)0.58 (.023)
2X01..7164 ((..003405))0.25 (.010) M A M B0.46 (.018)
2.28 (.090)NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
4.57 (.180) 2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).

Part Marking Information
TO-252AA (D-PARK)

EXAMPLE : THIS IS AN IRFR120
LWOITT H C AOSDSE E 9MUB1LPY INTERNATIONAL
A
FIRST PORTION
R ELCOTGIFOIERIRFROF PART NUMBER
0219U 1P
ASSEMBLYSECOND PORTION
LOT CODEOF PART NUMBER

8

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Package Outline
TO-251AA Outline
Dimensions are shown in millimeters (inches)
66..3753 ((..225605))
- A -5.46 (.215)01..8287 ((..005305))
5.21 (.205)
411..1552 ((..004650))56..2927 ((..224355))
1 2 3
- B -2.28 (.090)
1.91 (.075)89..8695 ((..335800))
1.14 (.045)
3X0.76 (.030)3X00..6849 ((..002355))
2.28 (.090)0.25 (.010) M A M B
X2

IRLR/U120N

22..1398 ((..008964))
0.58 (.023)
0.46 (.018)LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
56..6485 ((..222445)) 3 - SOURCE
4 - DRAIN
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
01..8194 ((..003455))
00..5486 ((..002138))

Part Marking Information
TO-251AA (I-PARK)
EXAMPLE : THIS IS AN IRFU120
WITH ASSEMBLY
LOT CODE 9U1PINTERNATIONALFIRST PORTION
RECTIFIERIRFUOF PART NUMBER
LOGO120
9U 1P
ASSEMBLYSECOND PORTION
LOT CODEOF PART NUMBER

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9

IRLR/U120N

Tape & Reel Information
TO-252AA

01

RT

1165..37 (( ..664119 ))

1112..91 (( ..447669 ))FEED DIRECTION78..91 (( ..331128 ))
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
23.. AOLULT DLIINMEE NCSOINOFNOS RAMRSE TSOH OEIWA-N4 8IN1 &M IELILAI-M54E1T.ERS ( INCHES ).

13 INCH

NOTES :
1. OUTLINE CONFORMS TO EIA-481.

TRRTRL

mm 61

1165..73 (( ..661491 ))

FEED DIRECTION

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S15a aLlibnucroglsnt rCasosuret , 1B5r7a, m6p1t3o5n0, BOantda rHioo mL6bTu r3g ZT2e, l:T +el+: (4990 56)1 7425 39 62529000
IR ITALY:
Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IIRR F SAOR UETAHSETA:

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Data and specifications subject to change without notice.5/98
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