Boundary-Scan Tutorial

Boundary-Scan Tutorial

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Description







Boundary-Scan Tutorial














Boundary-Scan Tutorial




See the ASSET homepage on the World Wide Web at
http://www.asset-intertech.com














ASSET, the ASSET logo and ScanWorks are registered trademarks, and DFT Analyzer is a trademark of
ASSET InterTech, Inc.

Windows is a registered trademark of Microsoft Corporation.













© 2007-2009, ASSET InterTech, Inc.
© 2007, R.G. Bennetts
ii Boundary-Scan Tutorial
Table of Contents
Introduction .............................................................................................................................................................. 5
Chapter 1: The Motivation for Boundary-Scan Architecture ............................................................................... 6
Chapter 2: The Principle of Boundary-Scan Architecture ................................................................................... 7
Using the Scan Path ................................................................................................................................................................. 7
Chapter 3: IEEE 1149.1 Device Architecture ....................................................................................................... 11
The Instruction Register ........................................................................................................................................................ ...

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     Boundary-Scan Tutorial                
    
ii
Boundary-Scan Tutorial
See the ASSET homepage on the World Wide Web at http://www.asset-intertech.com               ASSET, the ASSET logo and ScanWorks are registered trademarks, and DFT Analyzer is a trademark of ASSET InterTech, Inc.  Windows is a registered trademark of Microsoft Corporation.              © 2007-2009, ASSET InterTech, Inc. © 2007, R.G. Bennetts
 
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   Using the Scan Path .................................................................................................................................................................7  The Instruction Register..........................................................................................................................................................11 The Instructions ......................................................................................................................................................................12 Using the Instruction Register (IR)..........................................................................................................................................13 Use of the “Capture 01” Mode ................................................................................................................................................14 The Test Access Port (TAP) ...................................................................................................................................................15 The Bypass Register ..............................................................................................................................................................16 The Identification Register ......................................................................................................................................................17 Use of the lsb = 1 Feature ......................................................................................................................................................17 Boundary-Scan Register.........................................................................................................................................................19 Providing Boundary-Scan Cells ..............................................................................................................................................20 Accessing Other Core-Logic Registers ...................................................................................................................................21  General Strategy.....................................................................................................................................................................22 Interconnect Test Example .....................................................................................................................................................22 Practical Aspects of Using Boundary-Scan Technology .........................................................................................................24 Handling Non-Boundary-Scan Clusters ..............................................................................................................................24 Access to RAM Arrays ........................................................................................................................................................25 Other Issues of Boundary Scan-to-Non-Boundary Scan Interfacing...................................................................................26 Assembling the Final Test Program ....................................................................................................................................27 Tester Hardware .................................................................................................................................................................27 9 Boundary-Scan Description Language (BSDL).......................................................................................................................29 What Is BSDL? ...................................................................................................................................................................29 How BSDL is Used .............................................................................................................................................................29 Elements of BSDL ..............................................................................................................................................................29 Hierarchical Scan Description Language (HSDL) ...................................................................................................................31 What Is HSDL? ...................................................................................................................................................................31 HSDL Module Statements ..................................................................................................................................................31 Serial Vector Format (SVF) ....................................................................................................................................................32 What Is SVF?......................................................................................................................................................................32 SVF Structure .....................................................................................................................................................................33 Standard Test And Programming Language, STAPL .............................................................................................................36 What is STAPL? .................................................................................................................................................................36 Basic Structure of a STAPL program ..................................................................................................................................36 STAPL Composers, Players and Sessions.........................................................................................................................36 STAPL Program Example...................................................................................................................................................37 STAPL: final comments ......................................................................................................................................................39  Development of the IEEE 1532 Standard ...............................................................................................................................40 PLD Programming Environment .............................................................................................................................................40 PLD Programming Formats and Languages ..........................................................................................................................42 IEEE 1532 In-System Configuration Standard........................................................................................................................43 Accessing Program Data and Address Registers ...................................................................................................................44 IEEE 1532 Instructions ...........................................................................................................................................................45 Flows, Procedures and Actions ..............................................................................................................................................46 Conclusions ............................................................................................................................................................................47 To Probe Further … ................................................................................................................................................................48  What’s The Problem? .............................................................................................................................................................49 DC and AC-coupled Low-Voltage Differential Signals ............................................................................................................50 SERializer-DESerializer, SERDES, Structures .......................................................................................................................51 
Table of Contents
1  
Boundary-Scan Tutorial
 Table of Figures Figure 1: ICT versus Functional Test........................................................................................................................ 6 Figure 2: Principle of Boundary-Scan Architecture................................................................................................... 7 Figure 3: Using the Boundary-Scan Path ................................................................................................................. 7 Figure 4:  Basic Boundary-Scan Cell ......................................................................................................................... 8 Figure 5: Bed-of-Nails Fault Coverage ..................................................................................................................... 9 Figure 6: Boundary-Scan Fault Coverage (Intest 9) .................................................................................................... Figure 7: Boundary-Scan Fault Coverage (Extest)................................................................................................. 10 Figure 8: IEEE 1149.1 Chip Architecture................................................................................................................ 11 Figure 9: The Instruction Register .......................................................................................................................... 12 Figure 10: Using the Instruction Register — Step 1 ............................................................................................... 13 Figure 11: Using the Instruction Register — Step 3 ............................................................................................... 14 Figure 12: TAP Controller Global View ................................................................................................................... 15 Figure 13: TAP Controller State Table Diagram ..................................................................................................... 16 Figure 14: The Bypass Register ............................................................................................................................. 17 Figure 15: Device Identification Code Structure ..................................................................................................... 17 Figure 16: Use of the lsb = 1 Feature — Step 1 ..................................................................................................... 18 Figure 17: Use of the lsb = 1 Feature — Step 3 ..................................................................................................... 18 Figure 18: Basic Boundary-Scan Cell (Input) ......................................................................................................... 19 Figure 19: Basic Boundary-Scan Cell (Input/Output) ............................................................................................. 19 Figure 20: A Reason for the Hold State .................................................................................................................. 20 Figure 21: Control of Tristate Outputs .................................................................................................................... 20 Figure 22: Bidirectional Input/Output Pins .............................................................................................................. 21 
 Options for AC-Coupling Test .................................................................................................................................................53 IEEE 1149.6 Basic Architecture..............................................................................................................................................53 Conclusions ............................................................................................................................................................................56 To Probe Further … ................................................................................................................................................................56  Why Do We Need DFT Guidelines? .......................................................................................................................................57 Chip-Level DFT Guidelines.....................................................................................................................................................58 Board-Level DFT Guidelines ..................................................................................................................................................60 To Probe Further ....................................................................................................................................................................62 3 Product Life Cycle Issues .......................................................................................................................................................63 Design Debug .....................................................................................................................................................................63 Manufacturing Test .............................................................................................................................................................63 Field Test and Repair .........................................................................................................................................................64 Boundary-Scan Tools Requirements ......................................................................................................................................64 Design Debug .....................................................................................................................................................................65 Manufacturing Test .............................................................................................................................................................65 Field Test and Repair .........................................................................................................................................................67  IEEE P1687 (IJTAG) Initiative.................................................................................................................................................68 System JTAG (SJTAG) Initiative.............................................................................................................................................69 Boundary Scan and its Relationship with other Test Techniques ...........................................................................................69 Other New Standard Developments .......................................................................................................................................72 4   
 
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Boundary-Scan Tutorial
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Boundary-Scan Tutorial
 Figure 24: Interconnect Testing Solution ................................................................................................................ 23 Figure 25: Detecting the Fault................................................................................................................................. 23 Figure 26: Locating the Fault .................................................................................................................................. 24 Figure 27: Handling Non-Boundary Scan Clusters.................................................................................................. 25 Figure 28: Testing a RAM Array Via Boundary Scan ............................................................................................. 25 Figure 29: Boundary Scan-to-non-Boundary Scan Interface.................................................................................. 26 Figure 30: Assembling a Test Program - Tool Flow ............................................................................................... 27 Figure 31:  Tester Hardware .................................................................................................................................... 28 Figure 32: Programming a cPLD Through the Scan Chain ..................................................................................... 36 Figure 33: Background on In-System Configuration............................................................................................... 40 Figure 34: Programming the PLD Through the Scan Chain................................................................................... 41 Figure 35: PLD Programming Formats and Languages ......................................................................................... 42 Figure 36: Getting Programming Data to the PLD.................................................................................................. 42 Figure 37: IEEE 1532 - General Architecture ......................................................................................................... 43 Figure 38: IEEE 1532 - New Registers .................................................................................................................... 44 Figure 39: IEEE 1532 - Other New Registers (Optional) ........................................................................................ 44 Figure 40: Basic Program Memory Array Access................................................................................................... 44 Figure 41: Mandatory Instructions ........................................................................................................................... 45 Figure 42: Optional Programming Instructions ....................................................................................................... 45 Figure 43: Optional Program Control and Security Instructions .............................................................................. 46 Figure 44: Optional Address and Data Access Instructions ................................................................................... 46 Figure 45: Top-Level ISC Programming Flows, Procedures and Actions .............................................................. 47 Figure 46: IEEE 1532 - To Probe Further ............................................................................................................... 48 Figure 47: High-Speed Serial Buses - Application to PC Motherboard .................................................................. 49 Figure 48: PCI-Express Lane Architecture .............................................................................................................. 50 Figure 49: Differential DC Coupling ........................................................................................................................ 50 Figure 50: Differential AC Coupling ......................................................................................................................... 51 Figure 51: AC-Coupled SERDES Interconnects..................................................................................................... 51 Figure 52: Where Can Defects Occur?................................................................................................................... 52 Figure 53: Options for Testing AC-Coupled Interconnects ...................................................................................... 53 Figure 54: Interconnect Test: IEEE 1149.6 Solution .............................................................................................. 54 Figure 55: Modified TX Boundary-Scan Cell .......................................................................................................... 54 Figure 56: 1149.6 Test Receiver ............................................................................................................................ 55 Figure 57: New 1149.6 Instructions ........................................................................................................................ 55 Figure 58: IEEE 1149.6 - To Probe Further............................................................................................................ 56 Figure 59: Why Do We Need DFT Guidelines?...................................................................................................... 57 Figure 60: ASIC/SoC/SiP Chip-Level DFT Guidelines ........................................................................................... 58 Figure 61: Chip-Level DFT Guidelines: Some Examples ....................................................................................... 58 Figure 62: Chip-Level DFT Guidelines - Some More Examples............................................................................. 59 Figure 63: Board-Level DFT Guidelines ................................................................................................................. 60 Figure 64: Board-Level DFT Guidelines - Some Examples.................................................................................... 60 Figure 65: Board-Level DFT Guidelines - Some More Examples .......................................................................... 61 Figure 66: Board-Level DFT Guidelines - Yet More Examples .............................................................................. 62 Figure 67: DFT Guidelines - To Probe Further ........................................................................................................ 62 Figure 68: TAP Access to Embedded Instruments.................................................................................................. 68 Figure 69: Benchtop + In-Circuit Testers ................................................................................................................. 70 Figure 70: Accessing a Non-Boundary-Scan Cluster Using Nails........................................................................... 70