Design of fully integrated 60 GHz OFDM transmitter in SiGe BiCMOS technology [Elektronische Ressource] / vorgelegt von Srđan Glišić
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Design of fully integrated 60 GHz OFDM transmitter in SiGe BiCMOS technology [Elektronische Ressource] / vorgelegt von Srđan Glišić

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181 Pages
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Design of Fully Integrated 60 GHz OFDM Transmitter in SiGe BiCMOS Technology Von der Fakultät für Mathematik, Naturwissenschaften und Informatik der Brandenburgischen Technischen Universität Cottbus zur Erlangung des akademischen Grades Doktor der Ingenieurwissenschaften (Dr.-Ing.) genehmigte Dissertation vorgelegt von Diplom-Ingenieur Srñan Glišić geboren am 03.04.1976 in Sarajevo, Bosnien und Herzegowina Gutachter: Prof. Dr.-Ing. Rolf Kraemer Gutachter: Prof. Dr.-Ing. Hermann Schumacher Gutachter: Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel Tag der mündlichen Prüfung: 16. Dezember 2010. Acknowledgements Acknowledgements While working in the IHP’s Circuit Design department I had support from many colleagues. At this place I want to thank those who helped me with the thesis. First of all, I want to thank to my supervisor Prof. Rolf Kraemer who offered me the opportunity to work at IHP and supported my work ever since. I especially want to thank Dr. J. Christoph Scheytt who supported my work and was always available for many useful discussions. I wish to thank all my colleagues from the project and department for their help, useful discussions, support and friendship. I thank Dr. Wolfgang Winkler, Dr. Frank Herzel, Dr. Eckhard Graß, Mohamed Elkhouly, Dr. Prabir Datta, Dr. Yaoming Sun, Dr. Miloš Krstić, Miroslav Marinković, Johannes Borngräber, Maxim Piz, Dr.

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Published 01 January 2010
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Design of Fully Integrated 60 GHz OFDM
Transmitter in SiGe BiCMOS Technology


Von der Fakultät für Mathematik, Naturwissenschaften und Informatik
der Brandenburgischen Technischen Universität Cottbus

zur Erlangung des akademischen Grades

Doktor der Ingenieurwissenschaften

(Dr.-Ing.)

genehmigte Dissertation

vorgelegt von

Diplom-Ingenieur

Srñan Glišić

geboren am 03.04.1976 in Sarajevo, Bosnien und Herzegowina



Gutachter: Prof. Dr.-Ing. Rolf Kraemer

Gutachter: Prof. Dr.-Ing. Hermann Schumacher

Gutachter: Prof. Dr.-Ing. Dr.-Ing. habil. Robert Weigel

Tag der mündlichen Prüfung: 16. Dezember 2010.






Acknowledgements



Acknowledgements






While working in the IHP’s Circuit Design department I had support from many
colleagues. At this place I want to thank those who helped me with the thesis.
First of all, I want to thank to my supervisor Prof. Rolf Kraemer who offered me the
opportunity to work at IHP and supported my work ever since.
I especially want to thank Dr. J. Christoph Scheytt who supported my work and was always
available for many useful discussions.
I wish to thank all my colleagues from the project and department for their help, useful
discussions, support and friendship. I thank Dr. Wolfgang Winkler, Dr. Frank Herzel, Dr.
Eckhard Graß, Mohamed Elkhouly, Dr. Prabir Datta, Dr. Yaoming Sun, Dr. Miloš Krstić,
Miroslav Marinković, Johannes Borngräber, Maxim Piz, Dr. Chang-Soon Choi, Dr. Klaus
Schmalz, Dr. Gerhard Fischer, Falk Korndörfer, Markus Ehrig, Markus Petri and Frank
Popiela.
Želim na ovom mjestu da se zahvalim za svu ljubav i podršku koju sam imao od moje
majke i brata, a naročito za njihovu podršku za vrijeme mojih studija.
Finally, my love and gratitude go to my wife Izabela for her great help, support and love.
Writing this thesis was possible thanks to her constant support. My thanks go to my son
Adam, who brings me joy every day.

iii Glišić, Design of Fully Integrated 60 GHz OFDM Transmitter in SiGe BiCMOS Technology



iv Contents


Contents

Abstract ix
Zusammenfassung xi
Chapter 1. Intorduction 1
1.1. Wireless Communication at 60 GHz...............................................................................1
1.2. IHP’s SiGe:C BiCMOS Technology...............................................................................4
1.3. Thesis Objective and Organization .................................................................................5
Chapter 2. Transmitter Achitecture 7
2.1. Introduction .....................................................................................................................7
2.2. Application Scenarios and TX Requirements .................................................................7
2.2.1. Link Budget Calculation ..........................................................................................8
2.3. TX Topology ...................................................................................................................9
2.3.1. Version I TX Topology..........................................................................................10
2.3.2. Version II TX Topology.........................................................................................11
2.3.3. Version III TX Topology .......................................................................................11
2.3.4. Upconversion Mixer...............................................................................................12
2.3.5. Preamplifier............................................................................................................13
2.4. Summary........................................................................................................................14
Chapter 3. Phase–locked Loop 15
3.1. Introduction ...................................................................................................................15
3.2. PLL Theory ...................................................................................................................16
3.2.1. Type I PLL .............................................................................................................16
3.2.1.1. Type I PLL Components.................................................................................16
3.2.1.2. Type I PLL Operating Principle .....................................................................18
3.2.2. Type II PLL............................................................................................................20
3.2.2.1. Type II PLL Components ...............................................................................20
3.2.2.2. Type II PLL Linear Model..............................................................................23
3.2.2.3. Type II PLL Stability Analysis.......................................................................26
3.2.3. PLL Phase Noise Properties...................................................................................28
3.2.3.1. Phase Noise of the Input Signal......................................................................28
3.2.3.2. VCO Phase Noise ...........................................................................................29
v Glišić, Design of Fully Integrated 60 GHz OFDM Transmitter in SiGe BiCMOS Technology

3.2.3.3. LPF Noise....................................................................................................... 30
3.3. RMS Phase Error Optimization .................................................................................... 31
3.4. Calculation of PLL Parameters..................................................................................... 32
3.4.1. Parameter Calculation Recipe for a Third Order PLL........................................... 33
3.4.2. Parameter Calculation Recipe for a Fourth Order PLL......................................... 34
3.4.3. A New Parameter Calculation Recipe for a Fourth Order PLL............................. 37
3.5. Comparison of Different PLL Topologies.................................................................... 43
3.5.1. Dual Loop PLL...................................................................................................... 43
3.5.2. Comparison of a Third, Forth Order and Dual Loop PLLs ................................... 44
3.6. PLL for AFE version I .................................................................................................. 46
3.7. PLL for AFE version II................................................................................................. 49
3.8. Summary ....................................................................................................................... 50
Chapter 4. Image–rejection Filter 51
4.1. Introduction................................................................................................................... 51
4.2. Filter Design Theory ..................................................................................................... 51
4.2.1. Two–Port Network Characterization..................................................................... 52
4.2.2. Filter Parameters.................................................................................................... 53
4.2.3. Typical Filter Response Approximations .............................................................. 54
4.2.4. Lowpass Prototype Filters ..................................................................................... 55
4.2.5. Element and Frequency Transformation ............................................................... 58
4.2.6. Immittance Inverters.............................................................................................. 59
4.2.7. Filters with Immittance Inverters........................................................................... 62
4.2.8. Richards’ Transformation...................................................................................... 64
4.2.9. End–Coupled Microstrip Filters ............................................................................ 66
4.2.10. Parallel–Coupled Microstrip Filters................................................................... 68
4.2.11. Hairpin Microstrip Filters .................................................................................. 70
4.2.12. Selective Microstrip Filters with Transmission Zeros ....................................... 73
4.3. Filter Losses .................................................................................................................. 75
4.3.1. Effects of Filter Losses on the Lowpass Frequency Response.............................. 76
4.3.2. Effects of Filter Losses on the Bandpass Frequency Response............................. 77
4.3.3. Microstrip Filter Losses......................................................................................... 78
4.4. Design of the 60 GHz Image–Rejection Filter.............................................................. 79
4.4.1. Specifications of the Image–rejection Filter.......................................................... 79
4.4.2. The State–of–the–Art in 60 GHz Filters................................................................ 80
vi Contents

4.4.3. Filter Simulation and Substrate Definition ............................................................81
4.4.4. Filter Design...........................................................................................................82
4.4.4.1. Broadband Hairpin Filter ................................................................................84
4.4.4.2. Broadband Parallel–Coupled Asymmetrically Tuned Filter ..........................85
4.4.4.3. Parallel–Coupled Asymmetrically Tuned Filter for the IEEE 802.15.3c
Standard 87
4.4.4.4. Lumped Element Filter for the IEEE 802.15.3c Standard..............................88
4.4.4.5. Narrowband on–Board Filter ..........................................................................90
4.5. Summary........................................................................................................................91
Chapter 5. Power Amplifier 93
5.1. Introduction ...................................................................................................................93
5.2. Power Amplifier Theory................................................................................................94
5.2.1. Stability Considerations of an Amplifier............................................................94
5.2.2. Small-Signal Operation of an Amplifier ............................................................97
5.2.3. Amplifier Linearity.............................................................................................98
5.2.3.1. AM-AM Distortion and 1dB Compression Point.........................................100
5.2.3.2. AM-PM Distortion........................................................................................101
5.2.3.3. Intermodulation Distortion ...........................................................................101
5.2.4. Linearity of Cascaded Amplifiers ........................................................................102
5.2.5. Efficiency and PA Classes ...................................................................................103
5.2.6. Load-Pull Measurements..................................................................................105
5.2.7. Power Combining Techniques..........................................................................105
5.3. Modeling of Distributed Passive Elements for Matching ...........................................107
5.4. Power Amplifier Design in the 60 GHz Range ...........................................................109
5.4.1. PA System Requirements.....................................................................................109
5.4.2. PA Schematic Design...........................................................................................110
5.4.3. PA Layout and Post-layout Simulation................................................................115
5.5. Power Amplifier Measurement ...................................................................................118
5.5.1. Measurement Setup..............................................................................................118
5.5.2. Measurement Results ...........................................................................................120
5.5.3. Comparison with the State-of-the-Art..................................................................125
5.6. Summary......................................................................................................................127
Chapter 6. Transmitter Integration 129
6.1. Introduction .................................................................................................................129
vii Glišić, Design of Fully Integrated 60 GHz OFDM Transmitter in SiGe BiCMOS Technology

6.2. TX Integration and Board Design............................................................................... 129
6.3. Measurement Results .................................................................................................. 130
6.3.1. TX Version I Measurement Results .................................................................... 131
6.3.2. TX Version II Measurement Results ................................................................... 133
6.3.3. TX Version III Measurement Results.................................................................. 135
6.3.4. Link-Budget Calculation for the Version III AFE............................................... 138
6.4. Comparison with the State-of-the-Art......................................................................... 139
6.5. Summary ..................................................................................................................... 141
Chapter 7. Conclusons 143
References 147
List of Figures 153
List of Tables 159
Publications 161
List of Acronyms and Symbols 165
Curriculum Vitae 169
viii Abstract


Abstract






The goal of this thesis is the analysis of the challenges and finding solutions for the design
of mm-wave transceivers. The work presented here is focused on design of transmitter (TX)
components, which are critical for the performance of the whole analog front-end. Phase-
locked loop (PLL) phase noise is optimized, an image-rejection filter and a high 1 dB
compression point (P1dB) power amplifier (PA) are designed.
The PLL phase noise optimization is presented and different PLL topologies are compared.
A new optimized recipe for calculating PLL parameters of a forth order PLL is presented.
Using this approach the spurious sidebands can be reduced by up to 10 dB.
The image-rejection filter chapter analyzes the challenges related to the design of the
integrated image–rejection filter. The analysis presented here is the first on integrated filters
for the 60 GHz band, because the previously published work dealt with on-board filters. The
main problems related to the design of integrated filters arise from the low quality factor of
the integrated resonators. The effects are high insertion loss and low selectivity. Two
measures to reduce the insertion loss of the image–rejection filters were suggested. One is to
design the filter as broadband. This measure deteriorates selectivity, so the minimum required
image–rejection will limit the width of the passband. The second measure is to design the
filter as broadband with non-equidistant transmission zeros (i.e. asynchronously tuned filter).
This measure will improve both the insertion loss and the image–rejection.
The challenges related to the design of mm-wave PAs with high P1dB are analyzed and the
procedure of the PA design is presented. The difficulties related to the PA design and layout
are discussed and optimum solutions presented. Limits of different power combining
ix Glišić, Design of Fully Integrated 60 GHz OFDM Transmitter in SiGe BiCMOS Technology

techniques for integrated PAs are discussed. Effects of poor on-chip ground connection are
analyzed. Different causes for P1dB degradation are analyzed. The produced PA features a
differential cascode topology. The layout is symmetrical and presents a virtual ground on the
symmetry line for the differential signal. The optimized schematic and a symmetrically drawn
layout resulted in a 17 dBm measured P1dB. It was the highest reported P1dB in 60 GHz
SiGe PAs when it was published.
The fully integrated TX was used for data transmission with data rate of 3.6 Gbit/s (with
coding 4.8 Gbit/s) over 15 meters. This is the best result in the class of 60 GHz AFEs without
beamforming.

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