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Deterministic performance space exploration of analog integrated circuits considering process variations and operating conditions [Elektronische Ressource] / Daniel Müller-Gritschneder

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TECHNISCHEUNIVERSITÄTMÜNCHENLehrstuhlfürEntwurfsautomatisierungDeterministic Performance Space Explorationof Analog Integrated Circuits consideringProcess Variations and Operating ConditionsDanielMüller-GritschnederVollständiger Abdruck der von der Fakultät für Elektrotechnik und Informations-technik der Technischen Universität München zur Erlangung des akademischenGradeseinesDoktor-IngenieursgenehmigtenDissertation.Vorsitzender: Univ.-Prof. Dr. techn. JosefA.NossekPrüferderDissertation: 1. Priv.-Doz. Dr.-Ing. HelmutGräb2. Univ.-Prof. Dr.-Ing. LarsHedrich,JohannWolfgangGoethe-UniversitätFrankfurtamMainDie Dissertation wurde am 19.01.2009 bei der Technischen Universität Müncheneingereicht und durch die Fakultät für Elektrotechnik und Informationstechnikam26.06.2009angenommen.ApaperbackversionofthisthesiswaspublishedbyVerlagDr.Hut,Munich,in2009.ISBN978-3-86853-167-1.AcknowledgmentsThis work resulted from my five year long research activity at the Institute of Elec-tronic DesignAutomation of theTU München. First of all, I wantto thank Prof. UlfSchlichtmann for giving me the chance to conduct my research at his institute andassist in his lectures. I also want to thank Dr. Helmut Gräb for his guidance duringmyresearchwork. Hisadvice,feedbackandourdiscussionsaidedmegreatlyinde-veloping the ideas and methods presented in this work. I would also like to thankthe other committee members, Prof. Nossek and Prof.

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TECHNISCHEUNIVERSITÄTMÜNCHEN
LehrstuhlfürEntwurfsautomatisierung
Deterministic Performance Space Exploration
of Analog Integrated Circuits considering
Process Variations and Operating Conditions
DanielMüller-Gritschneder
Vollständiger Abdruck der von der Fakultät für Elektrotechnik und Informations-
technik der Technischen Universität München zur Erlangung des akademischen
Gradeseines
Doktor-Ingenieurs
genehmigtenDissertation.
Vorsitzender: Univ.-Prof. Dr. techn. JosefA.Nossek
PrüferderDissertation: 1. Priv.-Doz. Dr.-Ing. HelmutGräb
2. Univ.-Prof. Dr.-Ing. LarsHedrich,JohannWolfgang
Goethe-UniversitätFrankfurtamMain
Die Dissertation wurde am 19.01.2009 bei der Technischen Universität München
eingereicht und durch die Fakultät für Elektrotechnik und Informationstechnik
am26.06.2009angenommen.ApaperbackversionofthisthesiswaspublishedbyVerlagDr.Hut,Munich,in2009.
ISBN978-3-86853-167-1.Acknowledgments
This work resulted from my five year long research activity at the Institute of Elec-
tronic DesignAutomation of theTU München. First of all, I wantto thank Prof. Ulf
Schlichtmann for giving me the chance to conduct my research at his institute and
assist in his lectures. I also want to thank Dr. Helmut Gräb for his guidance during
myresearchwork. Hisadvice,feedbackandourdiscussionsaidedmegreatlyinde-
veloping the ideas and methods presented in this work. I would also like to thank
the other committee members, Prof. Nossek and Prof. Hedrich, for their interest in
mywork.
IthankmycolleaguesGuidoStehr,JunZouandHusniHabal,withwhomIworked
closelytogetherduringmyresearch. Ialsowanttothankallmyothercolleaguesthat
madethetimeattheinstituteinterestingandfun.
Finally,Iwanttoexpressmygratitudetowardsallmyfamily,mywifeVreni,mykids
Lukas, Teresa and Justus, my parents Wolfgang and Gabriele, my brothers Michael,
Patrick, David and Gabriel and my sister Magdalena as well as my family-in-law,
Bine, Benno, Nathalie, Matthias and Elisabeth, for their continuous support. I also
wanttothankmyfriendsofthe’Teestube’forallthegoodtimesduringtheseyears.Contents
1 Introduction 1
1.1 AnalogDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1 AnalogDesignFlow . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.2 ProcessVariationsandOperatingConditions . . . . . . . . . . . 2
1.1.3 CircuitPerformances . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.4 AutomaticCircuitSizingandAnalogSynthesis . . . . . . . . . 4
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1 PerformanceSpaceExploration . . . . . . . . . . . . . . . . . . . 5
1.2.2 PerformanceTrade-offAnalysisandCircuitStructure Selection 6
1.2.3 AutomaticHierarchicalSizing . . . . . . . . . . . . . . . . . . . 6
1.3 State-of-the-art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3.1 PerformanceSpaceExplorationMethods . . . . . . . . . . . . . 8
1.3.2 HierarchicalSizingMethods . . . . . . . . . . . . . . . . . . . . 10
1.3.3 ToleranceAnalysisMethods. . . . . . . . . . . . . . . . . . . . . 11
1.4 ContributionsofthisThesis . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5 PreviousPublications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 OrganizationofthisThesis . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Description of the Performance Space Exploration Task 15
2.1 BasicDefinitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1 CircuitParameters . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.2 CircuitPerformancesandSimulation . . . . . . . . . . . . . . . 16
2.1.3 SizingRulesandValidParameterSpace . . . . . . . . . . . . . . 17
2.1.4 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.5 ParametricYield . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 ThePerformanceSpaceExplorationTask . . . . . . . . . . . . . . . . . 19
2.2.1 FeasiblePerformanceSpace . . . . . . . . . . . . . . . . . . . . . 19
2.2.2 Multi-objectiveOptimizationandParetoOptimality . . . . . . 19
2.2.3 ParetoFront . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.4 WeakParetoOptimality . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.5 Application-DependentParetoFront . . . . . . . . . . . . . . . . 23
2.2.6 SpecificationParetoFront . . . . . . . . . . . . . . . . . . . . . . 23
2.2.7 Performance Space Exploration to Obtain a Discretized Pareto
Front . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
I3 Pareto Optimization 27
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1.1 Multi-ObjectiveOptimizationMethods . . . . . . . . . . . . . . 27
3.1.2 Approachestofinddifferentperformancecompromises . . . . 28
3.1.3 PresenceofweaklyPareto-optimalperformancevectors . . . . 29
3.1.4 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Goal-AttainmentandMinmaxMethod . . . . . . . . . . . . . . . . . . . 30
3.2.1 MinmaxMethod . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2.2 EquivalentGoal-AttainmentMethod . . . . . . . . . . . . . . . 31
3.2.3 PerformanceCompromiseattheOptimum . . . . . . . . . . . . 32
3.3 BasicsofParetoFrontGeneration . . . . . . . . . . . . . . . . . . . . . . 34
3.4 PerformanceSub-Spaces,Trade-OffLimitsandBoundaryofthePareto
front . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.1 PerformanceSub-Spaces . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.2 Trade-OffLimits . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.4.3 BoundaryoftheParetoFront . . . . . . . . . . . . . . . . . . . . 38
3.5 IterativeParetoFrontGenerationApproach . . . . . . . . . . . . . . . . 39
3.5.1 GenerationoftheDiscretizedParetoFrontforTwoPerformances 39
3.5.2 Generation of the Discretized Pareto Front for Three Perfor-
mances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.5.3 GenerationoftheParetofrontforAnyNumberofPerformances 41
3.5.4 Structure oftheIterativeParetoFrontGenerationApproach . . 43
3.6 Definition of Target Trajectories to Populate Inner Parts of the Pareto
Front . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.6.1 ProblemDescriptionforParallelTargetTrajectories . . . . . . . 45
3.6.2 CalculationoftheDirectionoftheTargetTrajectories . . . . . . 45
3.6.3 CompromiseWeightVectors . . . . . . . . . . . . . . . . . . . . 46
3.6.4 MappingofCompromiseWeightVectorsonBasePoints . . . . 47
3.6.5 CalculationoftheBasePointsbyLinearProgramming . . . . . 49
3.6.6 ComparisontoNormal-BoundaryIntersection . . . . . . . . . . 52
3.7 Iterative Pareto Front Generation Approach with Parallel Target Tra-
jectories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.7.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.7.2 Complexity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.8 Numericalexample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4 Wavefront Feasible Sequential Quadratic Programming 59
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.1.1 Standard Form oftheScalar ConstrainedNonlinearOptimiza-
tionProblem(CNOP) . . . . . . . . . . . . . . . . . . . . . . . . 59
4.1.2 MinmaxandGAFormulationintheStandardCNOPForm . . 59
4.1.3 SQPOptimizationAlgorithms . . . . . . . . . . . . . . . . . . . 60
4.1.4 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624.2 BasicsofSequentialQuadraticProgramming . . . . . . . . . . . . . . . 62
4.2.1 InitializationandUpdateoftheQuadraticModel . . . . . . . . 62
4.2.2 TheQuadraticProgram(QP) . . . . . . . . . . . . . . . . . . . . 64
4.2.3 BacktrackingLineSearch . . . . . . . . . . . . . . . . . . . . . . 64
4.3 FeasibleSQPAlgorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.3.1 TiltedQuadraticProgram . . . . . . . . . . . . . . . . . . . . . . 65
4.3.2 UpdateoftheTiltingVector . . . . . . . . . . . . . . . . . . . . . 67
4.3.3 ParallelLineSearchwithSecond-OrderCorrection . . . . . . . 68
4.3.4 FeasibilityFilterandCandidateSelection . . . . . . . . . . . . . 70
4.4 WavefrontApproach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.4.1 SimultaneousOptimization . . . . . . . . . . . . . . . . . . . . . 70
4.4.2 WavefrontFSQPAlgorithm . . . . . . . . . . . . . . . . . . . . . 72
4.4.3 StoppingCriteriaandActivenessofCNOPs . . . . . . . . . . . 72
4.5 ApplicationoftheMinmaxandGoal-AttainmentFormulation . . . . . 72
4.5.1 OptimizationwiththeMinmaxFormulation . . . . . . . . . . . 72
4.5.2 OptimizationwiththeGAFormulation . . . . . . . . . . . . . . 74
4.5.3 OptimizationwiththeGAandMinmaxFormulation . . . . . . 76
4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5 Pareto Optimization With Tolerances 79
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2 OptimizationBasedSpecificationAnalysis(SpA) . . . . . . . . . . . . . 80
5.2.1 OptimizationProblemoftheSpecificationAnalysis . . . . . . . 80
5.2.2 SpAandtheMinimumYieldRequirement . . . . . . . . . . . . 81
5.3 GenerationoftheSpecificationParetoFront . . . . . . . . . . . . . . . . 82
5.3.1 Multi-ObjectiveProblemFormulationConsideringTolerances . 83
5.3.2 GAandMinmaxFormulationConsideringTolerances . . . . . 83
5.3.3 RelationbetweentheSpecificationParetoFrontandtheNomi-
nalParetoFront . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.4 ChallengesintheComputationoftheSpecificationParetoFront 84
5.4 EfficientComputationoftheSpecificationParetoFront . . . . . . . . . 87
5.4.1 SpAafterParetoOptimization . . . . . . . . . . . . . . . . . . . 87
5.4.2 AlternatingSpAandParetoOptimization . . . . . . . . . . . . . 88
5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6 Experimental Results 93
6.1 TestCircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.1 OperationalTransconductanceAmplifier(OTA) . . . . . . . . . 94
6.1.2 CMOSOperationalAmplifiers(OpAmps). . . . . . . . . . . . . 94
6.1.3 VoltagedControlled5-StageRingOscillator(VCO) . . . . . . . 94
6.1.4 ChargePumpPhasedLockedLoop(CPPLL) . . . . . . . . . . . 95
6.2 ImplementationDetails. . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3 ComparisonofNovelIterativeandNBIApproachfortheOTA. . . . . 97
6.4 ComparisonofNovelIterativeandNBIApproachfortheVCO . . . . 996.5 EvaluationofWavefrontFSQPFeaturesfortheThreeOpAmps . . . . 101
6.6 EvaluationofWavefrontFSQPFeaturesfortheVCO . . . . . . . . . . . 105
6.7 ComparisonofWavefrontFSQPtoGeneralPurposeSQPfortheThree
OpAmps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.8 SpecificationParetoFrontfortheVCO . . . . . . . . . . . . . . . . . . . 110
6.9 SpecificationParetofrontforoneOpAmp . . . . . . . . . . . . . . . . . 111
6.10 ApplicationExamples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.10.1 SelectionofOpAmpStructure . . . . . . . . . . . . . . . . . . . 115
6.10.2 DevelopmentofaTrade-offBehavioralModelFortheVCO . . 115
6.10.3 Trade-offanalysisforaCPPLL . . . . . . . . . . . . . . . . . . . 117
7 Conclusion 119
A Pareto Optimization with Weakly Pareto-Optimal Performance Vectors 123
Bibliography 125
Nomenclature 135
Lists 139
ListofFigures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
ListofTables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141Chapter 1
Introduction
Recentyearshaveshownacleartrendinintegratedcircuit(IC)designtoimplement
functionality by meansof digital hardware. Still, there is a growing needfor analog
circuitry. Real world signals are analog. Digital circuits need analog interfaces and
analog-to-digital as well as digital-to-analog (AD/DA) converters to communicate
withtherealworld. Additionally,analogcircuitsareusedinpowermanagementand
clock generation ofdigital circuits aswellasfor RFsignalprocessing tasks. Modern
mixed-signal system-on-chip (SoC) solutions implement the digital circuit together
+with analog blocks on one single chip [KCJ 00]. This requires the design of ana-
log circuit blocks with the same digital complementary metal-oxide-semiconductor
(CMOS) technology. Digital CMOS technologies have shown a constant rate of de-
vice shrinking and decreasing supply voltage in recent years. Due to device shrink-
ing, more transistors can be realized on the same area, as described in the famous
forecastbyGordonMooreknownas’Moore’sLaw’[ITR06].
Thenumber of transistors inanalog circuits is usually only a fraction of thenumber
of transistors in digital circuits. Still, analog circuit design poses a major challenge
and can be the bottleneck in SoC design. Due to the many physical effects and per-
formancetrade-offs inanalogdesign,theintroduction of higherabstraction levelsis
difficult. Manyanalogcircuitsarestilldesignedmanuallybylookingatthecircuitat
transistorlevel.
Currently, research in analog electronic design automation (EDA) has focused on
automating analog design steps as well as to add hierarchy to the analog de-
sign flow. New design tools for circuit optimization are commercially available
[Mar01, MAW07]. Hardware description languages (HDL), such as VHDL-AMS
[APT02,DV03]andVerilog-A[VLR],canbeusedtodescribeanalogcircuitsonhigher
abstraction levels. Still, the analog design flow is lacking behind the digital flow in
termsofautomation, offeringachallengingfieldforthedevelopmentofnewdesign
methodologiesforanalogandmixed-signalcircuits.
11 Introduction
1.1 Analog Design
1.1.1 Analog Design Flow
The analog design flow for CMOS circuits can be broken into three steps [CGRS96,
Sch02,Gra07]:
1.Circuit structure (topology) generation or selection: First, a circuit structure, also
knownastopology,mustbegenerated. Often,onecanstartfromexistingtopolo-
gies(structure reuse).
2.Circuit sizing: One or more device parameters have to be chosen for each device
of the analog circuit. This step is known as circuit sizing. The selectable device
parameters are known as design parameters or sizing parameters. For example,
CMOStransistors aredescribedbytheirsize,whichisdefinedbythelengthand
widthofthechannel.
3.Layout generation: Finally, a layout must be generated for the sized circuit. The
layoutholdsthegeometricinformationrequiredtoproducetheintegratedcircuit
insilicon.
Figure 1.1illustrates the analog designflow. This thesis focuses on thecircuit sizing
step.
TopologyGeneration CircuitSizing LayoutGeneration
Figure1.1: Theanalogdesignflow
1.1.2 Process Variations and Operating Conditions
Somedeviceparametersaresubjecttostatistical variancesduetoinaccuraciesinthe
production process of integrated circuits. These process variations often have great
impact onthe electricalbehavior of the circuit. Shrinking devicesizesleadto arela-
tiveincreaseoftheimportanceofprocess variations, sincetheabsolute variations in
thedeviceparametersdonotscaledownbythesamefactorasthedevicesizes. Addi-
tionally,environmentalconditionssuchastemperatureaffecttheelectricalproperties
ofthecircuitduringoperation.
Theprocess variations andoperating conditions - inthefollowing referredto as tol-
erances - must be considered during the design phase of analog circuits. The circuit
sizingstepisseparatedintonominalsizingandtolerancesizing.
2