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Robust design of DRAM core circuits [Elektronische Ressource] : yield estimation and analysis by a statistical design approach / Yan Li

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Published 01 January 2010
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TECHNISCHE UNIVERSITÄT MÜNCHEN

Lehrstuhl für Technische Elektronik



Robust Design of DRAM Core Circuits
- Yield Estimation and Analysis
by A Statistical Design Approach


Yan Li


Vollständiger Abdruck der von der Fakultät für Elektrotechnik und Informationstechnik
der Technischen Universität München zur Erlangung des akademischen Grades eines

Doktor-Ingenieurs
genehmigten Dissertation.




Vorsitzender: Univ.-Prof. Paolo Lugli, Ph.D.
Prüfer der Dissertation:
1. Univ.-Prof. Dr. rer. nat. Doris Schmitt-Landsiedel
2. Univ.-Prof. Dr.-Ing. Roland Thewes,
Technische Universität Berlin




Die Dissertation wurde am 20.05.2009 bei der Technischen Universität München eingereicht und
durch die Fakultät für Elektrotechnik und Informationstechnik am 29.01.2010 angenommen. Preface
The information technology (IT) has been developing at an unimaginable speed
in the recent two decades and we are witnessing great changes in electronic de-
vices and related industries such as automobile, telecommunication and com-
puter. As the semiconductor device scaled down from several micrometers to
tens of nanometers and more performance circuitries are expected to appear so
as to increase the volume/bandwidth/speed of fundamental hardwares that IT
industry demands, traditional circuit design methodology is no longer capable of
covering all aspects required to meet the ever increasing requirements, especially
some coming from statistical views. As an example, only with the aid of modern
noise modeling and frequency domain system analysis can the communication
circuits and systems keep up with the fast changing pace anticipated.
For high volume memories, the production yield is facing a similar challenge.
On one hand, the ever increasing bit density emphasizes the signi cance of circuit
yield. On the other hand, design for yield of memory circuits is in an embarrassing
situation since until now there is no widely accepted methodology. As a conse-
quence, more e orts have to be taken in back-end testing and measurements. In
this dissertation, analytical yield analysis of DRAM core is carried out based on
traditional small signal circuit analysis, probability theories and Gaussian ap-
proximations. It has superior computation speed and accuracy. In order to verify
the model, it is applied to several designs and shows good agreements with sili-
con measurements. It is promising to pave the way for yield design, testing and
optimization of other memory devices and circuits.
The text comprises 7 chapters.
Chapter 1 provides some fundamental aspects on DRAM. 2 discusses in detail the signal amplitude loss and several interfer-
ences caused by array parasitics during sensing for di eren t array structures. It
is necessary to obtain the signal amplitude since the mean value and variance
determine the yield together.
Chapter 3 introduces di eren t sensing schemes and sense ampli ers. As the
focus of this work, CMOS latched sense ampli er is highlighted and its sensing
behavior, speed, power consumption and load sensitivity are studied.i
Chapter 4 introduces the basics of the analytical yield analysis method with
Gaussian approximations. As part of DRAM core yield design and an example
of using the analytical method, the mismatch of CMOS latched sense ampli ers
is modeled statistically.
Chapter 5 describes the leakage e ects in DRAM cells. Some mathematic
and probability transformations are made here, in order to obtain the leakage
induced yield degradation.
Chapter 6 presents a new overall statistical model and an analytical expres-
sion for DRAM core yield. Based on design examples, the validity and applica-
bility of the model are demonstrated.
Chapter 7 summarizes the work done in this dissertation.Acknowledgment
Beginning a Ph.D career is a brand-new life experience, always full of happiness,
excitement, also unexpected frustrations and disappointments. It all started with
a blank page, which is eventually lled with all kinds of colorful prints with the
elapse of time. For many times I wondered and puzzled in the face of setbacks
and di culties. Thanks to the help of these people, I can nally reach the goal.
The rst person I appreciate is my professor, Dr. rer. nat. Doris Schmitt-
Landsiedel. It is her that o ered me the opportunity to study my favorite mi-
croelectronics in Germany and she took care of my research progress whenever
possible. I also feel very lucky to be guided by Dr. Roland Thewes (Qimonda AG)
who gave me complete freedom in planning and scheduling my topic, while pro-
viding many suggestions to my work. My advisors, Helmut Schneider (Qimonda
AG) and Florian Schnabel (Qimonda AG) rstly led me into the DRAM world.
They provided me DRAM knowledge and practical design considerations that
are invaluable to the progress of this work. The dissertation also bene ted from
many individuals: Harald Roth (Qimonda AG), Michael Specht (Qimonda AG),
Jurgen Lindolf (Qimonda AG), Yipin Zhang (Qimonda AG), and those who gave
me opinions and suggestions. Thank you for your help.
In addition, I want to express my thanks to my colleges Marcus Weis, Philip
Teichmann, Jurgen Fischer, Markus Becherer, Mohamed Abdallah, Thomas Fis-
cher, Michael Flude, Rainer Emling, Florian Chouard, Matthias Eireiner, Andrea
Merkle, Agnese Bargagli-Sto and those in the Lehrstuhl Technische Elektronik
(LTE) who assisted me in my daily life and institute work.
Finally, I am grateful to my wife Lily and our parents. Their supports and
expectations provide the most powerful strength and courage to overcome all the
di culties on the way. Without them, I will never succeed.
I thank you all.
iiContents
Preface
Acknowledgment i
List of Symbols vii
Conventions ix
1 DRAM Fundamentals 1
1.1 Dynamic Random Access Memory (DRAM) . . . . . . . . . . . . 1
1.2 DRAM Chip Overview . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Sensing Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.1 Voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4.2 Current sensing . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4.3 Charge sensing . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 Sensing Failures and Yield . . . . . . . . . . . . . . . . . . . . . . 10
1.5.1 Yield experiments . . . . . . . . . . . . . . . . . . . . . . . 10
1.5.2 Number of experiments . . . . . . . . . . . . . . . . . . . . 11
1.5.3 Con dence region . . . . . . . . . . . . . . . . . . . . . . . 12
1.6 Motivation and Challenges . . . . . . . . . . . . . . . . . . . . . . 13
2 DRAM Core Array 16
2.1 DRAM Cell and Pre-sensing . . . . . . . . . . . . . . . . . . . . . 16
2.1.1 Pre-sensing speed . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.2 Developed bitline voltage amplitude . . . . . . . . . . . . . 19
ivCONTENTS v
2.2 Array Structures and Array Parasitics . . . . . . . . . . . . . . . . 20
2.2.1 Array parasitic e ect . . . . . . . . . . . . . . . . . . . . . 20
2.2.2 Array structures . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.3 Evaluation of developed bitline voltage in pre-sensing . . . 30
2.3 Post-sensing Crosstalk Coupling . . . . . . . . . . . . . . . . . . . 34
2.3.1 Cross-talk coupling with non-latched sense ampli ers . . . . 34
2.3.2 with latched sense ampli ers . . . . . . 37
2.3.3 Array structures and post-sensing coupling . . . . . . . . . 42
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3 DRAM Sense Ampli er and Sensing Techniques 45
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2 Low-, Mid- and High-Level Sensing . . . . . . . . . . . . . . . . . 46
3.2.1 NMOS sense ampli ers . . . . . . . . . . . . . . . . . . . . 46
3.2.2 CMOS sense . . . . . . . . . . . . . . . . . . . . 48
3.3 CMOS Latched Sense Ampli er . . . . . . . . . . . . . . . . . . . 50
3.3.1 Operation and sensing speed . . . . . . . . . . . . . . . . . 51
3.3.2 In uence of tail switches on post-sensing speed . . . . . . . 56
3.3.3 O set caused by imbalanced load capacitance . . . . . . . . 59
3.3.4 Array power consumption and power e ciency . . . . . . . 61
3.3.5 Sensing transistors leakage control . . . . . . . . . . . . . . 66
3.3.6 Transistor sizing and layout . . . . . . . . . . . . . . . . . 67
3.4 Charge Transfer Sense Ampli er . . . . . . . . . . . . . . . . . . . 68
3.5 Threshold Voltage Compensation Technique . . . . . . . . . . . . 72
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
4 Sense Ampli er Yield Analysis 75
4.1 Circuit Yield Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.1.1 Variation transfer . . . . . . . . . . . . . . . . . . . . . . . 76
4.1.2 Analytical yield expression . . . . . . . . . . . . . . . . . . 79
4.2 Random Error Sources in DRAM . . . . . . . . . . . . . . . . . . 80
4.3 Latched Sense Ampli er Yield Analysis . . . . . . . . . . . . . . . 81vi CONTENTS
4.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.3.2 Mismatch Equivalent o set V . . . . . . . . . . . . . . . . 81os
4.3.3 Yield optimization for mid-level sensing . . . . . . . . . . . 85
4.3.4 Switch delay induced yield degradation . . . . . . . . . . . 86
4.3.5 Comparisons with SPICE simulations . . . . . . . . . . . . 88
4.3.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5 Leakage Induced Yield Degradation 91
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.2 Leakage in DRAM Array . . . . . . . . . . . . . . . . . . . . . . . 91
5.3 Statistical Analysis of Leakage E ects . . . . . . . . . . . . . . . . 92
5.3.1 Sensing process with leakage . . . . . . . . . . . . . . . . . 92
5.3.2 Yield plot without retention time . . . . . . . . . . . . . . 93
5.3.3 Yield degradation with retention time . . . . . . . . . . . . 94
5.3.4 E ect of multiple leakage sources . . . . . . . . . . . . . . 98
5.4 MC Simulations vs. Measurements . . . . . . . . . . . . . . . . . . 100
5.4.1 Sensing yield vs. Initial cell voltage . . . . . . . . . . . . . 101
5.4.2 Data retention plot . . . . . . . . . . . . . . . . . . . . . . 106
5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6 DRAM Core Yield Analysis and Optimization 109
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.2 Statistical Linear Sensing Process . . . . . . . . . . . . . . . . . . 110
6.3 Yield Estimation vs. Measurements . . . . . . . . . . . . . . . . . 115
6.3.1 Arrays with di eren t cell capacitors . . . . . . . . . . . . . 116
6.3.2 Long vs. Short bitline arrays . . . . . . . . . . . . . . . . . 116
6.4 Yield Estimation for Future DRAM Core . . . . . . . . . . . . . . 117
2 2 26.4.1 8F , 6F and 4F arrays . . . . . . . . . . . . . . . . . . . 117
6.4.2 Sense ampli er optimization . . . . . . . . . . . . . . . . . 117
6.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7 Conclusions and Outlook 120List of Symbols
, , constants used to de ne capacitance matrix C
threshold voltage di erence in a pair of transistorsVth
, v of a pair of n- or p- transistorsVthn Vthp
coe cien t used to evaluate V for special array patternssign
C capacitance matrix used to evaluate bitline voltage of an array
Q charge matrix used to evaluate bitline voltage of an array
F failure probability
Y, Y’ theoretical and experimental yield probability
0 , , 0 mean value of V , V and Vva vb v a a b a
mean value of a statistical variable
, standard deviation of band to band energy gapEq Eq;m
of Vvos os
standard deviation of threshold voltagevth
, of v of n- or p- transistorsvthn vthp
, , , standard deviations of statistical variables1 2 3
constant used to caculate sub-Vt leakage current of a transistor
a , a linear coe cien ts related to a DRAM leakage source0 1
A, A small signal voltage gain0
C bitline to ground parasitic capacitance (w/o C and C etc.)bl bl2bl bl2wl
C to bitline capacitancebl2bl
C coupling capacitor between bitlinescpl
C dummy bitline capacitancedum
C parasitic capacitancei
C load of a sense ampli erl
C DRAM cell capacitors
0C bitline capacitance per unit lengthbl
0C to bitline coupling capacitance per unit lengthbl2bl
0C bitline to capacitance per cellbl2wl
E , E band to band energy gapq q;m
F minimum feature size for a DRAM technology
g small signal drain source transconductance of a transistords
g input transconductance of a transistorm
g , g input transconductances of n- and p-transistorsmn mp
I gate induced drain leakage currentGIDL
I , I , I reverse biased pn junction leakage in DRAM cellj j1 j2
I average of Ileak;m leak
I total leakage current of a DRAM cell storage nodeleak
I sub threshold leakage current of cell transistorsub
k , k coe cien ts to calculate V in multiple twisted arrays0 1 sign
K post-sensing coupling coe cien t used in signal margin analysiscpl
vii