FPGA Block Modular Design Tutorial
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FPGA Block Modular Design Tutorial

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‹‹‹FPGA Block Modular Design TutorialIntroductionThis tutorial describes the Block Modular Design (BMD) methodology and relative tools in ispLEVER that assist distributed teams in collaborating on large FPGA designs. BMD can also be employed as part of a incremental design strategy that is especially effective when isolated changes to a design are required and there is a need to minimize the impact to other modules in the design.In this tutorial you will implement a small Verilog HDL design that will be partitioned between a top-level project and two sub-module projects. Throughout the tutorial you will act both in the role of the team leader and a team member. As the team leader, you will be responsible for the organization and management of the overall project and its files, area and resource budgeting, and final assembly of all modules in the top-level project. In the role of a team member, you will be responsible for preparing sub-modules for final assembly, that is, implementing each sub-module in its own child project to create physical design (.ncd) files. Team members must coordinate their sub-module designs based on the resources and timing objectives assigned by the team leader.Learning ObjectivesWhen you have completed this tutorial, you should be able to:Understand and follow the recommended team methodology for a team to collaborate on a large FPGA design.Partition and budget logic resources for multiple sub-modules.Define the ...

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Introduction
FPGA Block Modular Design Tutorial
This tutorial describes the Block Modular Design (BMD) methodology and relative tools in ispLEVER that assist distributed teams in collaborating on large FPGA designs. BMD can also be employed as part of a incremental design strategy that is especially effective when isolated changes to a design are required and there is a need to minimize the impact to other modules in the design. In this tutorial you will implement a small Verilog HDL design that will be partitioned between a top-level project and two sub-module projects. Throughout the tutorial you will act both in the role of the team leader and a team member. As the team leader, you will be responsible for the organization and management of the overall project and its files, area and resource budgeting, and final assembly of all modules in the top-level project. In the role of a team member, you will be responsible for preparing sub-modules for final assembly, that is, implementing each sub-module in its own child project to create physical design (.ncd) files. Team members must coordinate their sub-module designs based on the resources and timing objectives assigned by the team leader. Learning Objectives When you have completed this tutorial, you should be able to: ‹Understand and follow the recommended team methodology for a team to collaborate on a large FPGA design. ‹Partition and budget logic resources for multiple sub-modules. ‹Define the relative location of the data paths between sub-modules.
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Introduction
‹Establish location and timing objectives for the top-level design. ‹Archive and deploy sub-module projects. ‹Implement a sub-module project. ‹Perform incremental verification of the top-level project. ‹Assemble and verify the top-level project. Time to Complete This Tutorial The time to complete this tutorial is about 45 minutes. System Requirements This section lists following software requirements, installation configurations, and software versions used in this tutorial. To run this tutorial successfully through completion, ensure that you have the following: ‹Installed version of ispLEVER software version 5.0 SP1 or higher. ‹Installed ispLEVER or ispLEVER Starter software package with active licenses for Mentor Graphics Precision RTL Synthesis or Synplicity Synplify with Verilog HDL support. ‹At least the OEM version of Mentor Graphics Precision or Synplicitys Synplify for synthesis of HDL source files. The body of the tutorial uses the Precision synthesis flow and alternate procedures for the Synplify synthesis flow are given in the appendix. ‹You must use the tutorial design files in thebmd_tutor.zipfile in the <install>\examples\tutorialfolder after installation of ispLEVER. This tutorialbmd_tutor.pdffile you are using is located in the <install>\ispcpld\tutorialdirectory path. ‹This tutorial is PC-based; however, it can also be run on UNIX/Linux if you are familiar enough with the ispLEVER interface on both platforms. About the Tutorial Design The tutorial design is a small data path design featuring one sub-module named (multreg16) with a multiplexer, multiply, with a registered output followed by another register stage named (rotate) that provides an optional rotate function."Block Diagram of the Tutorial Design"on page 3 provides a high level block diagram of the system.
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Figure 1: Block Diagram of the Tutorial Design
FPGA Block Modular Design Tutorial
Introduction
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Introduction
The Block Modular Design Methodology This section describes the Block Modular Design (BMD) methodology and its major process steps. The tutorial follows this approach, either taking you though each procedure step-by-step, or providing you with a finished input for illustrative purposes. The following is brief overview of each step: Step 1: Block Modular Design EntryIn the first step, the top-level design is written in HDL and each sub-module is instantiated along with synthesis compiler directives to treat them as black-boxes. The team leader should take special consideration that each design module is a good sub-module candidate. The ispLEVER online help provides guidelines on this topic. See theBlock Modular Design Step Guidethe FPGA Flow Help system and thein Block Modular Design Wizard Help system.In the tutorial, this step is already completed for you as these source Verilog HDL design files are supplied. Step 2: Block Modular Design SynthesisIn the second step, the RTL of each sub-module is synthesized. This step can be performed in parallel with or before Step 3; however, the device resource utilization report generated by logic synthesis will help ease the team leaders task of budgeting area size and region for each sub-module in Step 3.The tutorial guides you through synthesis of the top-level and sub-module designs using Precision RTL Synthesis and Synplify.Synplify synthesis flow procedures are given in the appendix. Step 3: Top-Level Block Module ConfigurationDuring Step 3, the team leader budgets logic resources and the location of each sub-module on the target device floorplan. The size and location of each sub-module must accommodate the synthesized logic produced in Step 2. Timing constraints are initially defined in this step. Global device resources like I/Os and PLLs are also assigned at this point. The team leader should adhere to the configuration requirements described in ispLEVER online help in the Top-Level Design Configuration Requirements topic in theBlock Modular Design Step Guidein the FPGA Flow Help.In the tutorial, preferences are already set for you in a supplied preference file and can be viewed to illustrate how a designer takes existing area and resource considerations into account. Step 4: Block Module ImplementationIn Step 4, each sub-module is implemented by respective team members concurrently to produce physical design (.ncdbe merged next step, that is, final assembly. The top-) files to level or parent project lends its logical translated netlist (.ngo) file and logical preference (.lpf) file to guide this process. Each sub-module is implemented into.ncdfiles ready for final assembly with other sub-modules and the top-level project. Timing objectives established in Step 3 by the team leader are applied and often extended by the team member responsible for the sub-module.The tutorial guides you through this step. Step 5: Block Modular Design AssemblyIn the final assembly step, the top-level and all sub-modules are merged together into one design.The tutorial guides you through this step.
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Introduction
The Tutorial Process Flow This section describes the sequence of processors and major data files you will apply during the tutorial tasks. The tutorial tasks lead you through the typical routine within the ispLEVER design environment to follow the BMD methodology described earlier.
Figure 2: Top-Level Process Flow
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Figure 3: Sub-Module Process Flow
Introduction
Before You Begin Before beginning, you must set up the tutorial design files to be used with this tutorial. To work with this tutorial, please take the following steps: 1. Go to the<install_dir>\examples\tutorial\b _ create ary nd md tutordirecto a directory called ispLEVER to work with this tutorial. Please note that you can set up your tutorial directory anywhere you wish; however, this tutorial will instruct you to this file path in procedures. All files in this ispLEVER folder will be consistent in a relative manner to whatever file path you use to run this tutorial, that is, all recursive directories and files should be the same. _ ir>\examp es\tut _folder, open the 2. In the tutor l orial\bmd<install d bmd_tutor.zipto the same directory path or to thefile and extract the files bmd tutor folder. _ Restoring the Tutorial InstallationAfter running through this tutorial one time, you may want to repeat it or allow someone else to run it locally or over the network. To restore the original state of the tutorial installation, remove _ contents of the ispLEVER sub-directory you created in thebmd tutor directory. The original source files for this tutorial will remain undisturbed in thebmd_tutor.zipfile in the source directory in _ es\t.\ex p am l utorial\bmd tutor.
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Task 1: Top-Level Module Design Entry and Synthesis
Task 1: Top-Level Module Design Entry and Synthesis In this task, you act in the role as the team leader and examine a pre-defined top-level tutorial design using Synplicity Synplify Pro for Lattice. The top-level design is written in Verilog HDL and each sub-module is instantiated along with synthesis compiler directives to treat each as a black-box. Black boxes are passed into the EDIF netlist as-is with no internal logic defined. "Block Diagram of the Tutorial Design"on page 3 illustrates the top-level organization and sub-module interconnect between sub-modulesmultreg16 androtate. Top-Level Synthesis with Synplify Pro for Lattice Use the following procedure to synthesize the design using Synplify Pro for Lattice. To create a Synplify project, inspect the top-level design, and synthesize it to EDIF: 1. From the Start menu, selectPrograms > Lattice Semiconductor > Accessories > Synplify Pro for Lattice. The Synplicity Synplify Pro for Lattice interface appears. 2. SelectFile > New Project. A default project Temp.prj appears and defaults to save to some location on your local hard disk.
3. On the button bar on the left of the Project View, click theAdd Filebutton. The Select Files to Add to Project dialog appears. 4. Browse to the..\examples\tutorial\b _folde , md tutor tor control-click select both theveriloghdsn.vandLatticeEC_66 _les, MHz PLL.vfi click <- Add, and then clickOK.
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Task 1: Top-Level Module Design Entry and Synthesis
5. In the Project View, expand the project hierarchy and drag and drop the veriloghdsn.vhdto the bottom of the Verilog folder file list. Note thatfile your project device could show a previous implementation. Ignore this. We will specify our target device later in the procedure.
6. Create a folder...\examples\tutorial\bmd tutor\synplify\veriloghdsn. _ 7. In Synplify Pro, selectFile > Save. The Save As dialog appears. md tutor\s n 8. Browse to the...\examples\tutorial\b _ y plify\veriloghdsn folder, specifyveriloghdsn.prj, and clickSave.
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Task 1: Top-Level Module Design Entry and Synthesis
9. Click on the Implementation Options button. An Implementation dialog for the veriloghdsn project rev_1 appears.
10. In the defaultDevicetab, select the following settings: ‹Technology:LatticeECP ‹Part:LFECP6E ‹Speed Grade:-4 ‹Package:T144I 11. Click the Implementation Results tab in the dialog and select the following: ‹Results Directory: ...\examples\tutorial\bmd_tutor\isplever\veriloghdsn ‹Result File Name:veriloghdsn.edn 12. ClickOK. 13. In the Project View, expand your project hierarchy under the Verilog tab and double click onveriloghdsn.vto open the file. The top-level Verilog module appears in the Text Editor. 14. Page down to the module declarations formultreg16androtate. Make note of the Synplify compiler directives added to the module declarations of multreg16 and rotate. T sy _ _ he  n black box command directs the compiler to pass the module instance untouched into the EDIF netlist.  module multreg16(q, dataa, datab, datac, sel, clk, rst)  / synthesis syn black box */; * _ _  output [15:0] q;  input [7:0] dataa, datab, datac;  input clk /* synthesis syn isclock = 1 */; _  input sel, rst;  reg [15:0] q;  endmodule
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Task 1: Top-Level Module Design Entry and Synthesis
_  module rotate(q, data, clk, r l, rst) _ _  /* synthesis syn black box */;  output [15:0] q;  input [15:0] data;  input clk /* synthesis syn isclock = 1 */; _ _  input r l, rst; 15. Click theRunbutton. Synplify creates an output EDIF netlist (veriloghdsn.edn) for the implementation. 16. In theImplementation ResultsView, double click theveriloghdsn.edn file. The netlist opens in the text editor.
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Task 2: Sub-Module Design Entry and Synthesis
Task 2: Sub-Module Design Entry and Synthesis In this task, you will act in the role of a team member responsible for the design of a sub-module. You will synthesize the tutorial HDL source files for each sub-module. In this scenario you define and optionally debug sub-module logic that is independent of the top-level design or other sub-modules. After synthesis you will use the utilization report of the compiler to make a rough estimate of the FPGA resources that will be required to accommodate the sub-module. This information will help the team leader make a better choice about location and size of the sub-module on the device floorplan. Sub-Module Synthesis of multreg16 with Synplify Pro Use the following procedure to synthesize the design using Synplify. To create a Synplify project for the sub-module and synthesize it to EDIF: 1. If Synplify is not already running, from the Start menu, selectPrograms > Lattice Semiconductor > Accessories > Synplify Pro for Lattice. The Synplicity Synplify for Lattice interface appears. 2. SelectFile New Project. > 3. A default project proj.temp appears. 4. Click theAdd Filebutton. The Select Files to Add to Project dialog appears. _ orfolde , electmultreg16.v, click<- Add, and 5. Browse to the.\bmd tutr s then clickOK. 6. Create a folder...\examples\tutorial\bmd_tutor\synplify\multreg16. 7. SelectFile > Save. The Save As dialog appears. 8. Browse to the...\examples\tutorial\bmd tutor\synplify\multreg16 _ folder, specifymultreg16.prj, and clickSave. 9. Click on the Implementation Options button. An Implementation dialog for the multreg16 project rev_1 appears. 10. In the defaultDevicetab and select the following: ‹Technology: LatticeECP ‹Part: LFECP6E ‹Speed Grade: -4 ‹Package: T144I ‹Device Mapping Options: Disable I/O Insertion (Enable) 11. Click the ImplementationResultstab in the dialog and select the following: ‹Results Directory: ...\examples\tutorial\bmd_tutor\Synplify\multreg16 ‹Result File Name:multreg16.edn 12. ClickOK. 13. Select themultreg16.prjproject in the Project View.
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