tutorial-clock
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Power Reduction Techniques in the SoCClock NetworkLow Power Design for SoCs ASIC Tutorial SoC Clock.1 ©M.J. Irwin, PSU, 1999Clock Powerl Why clock power is important/large» Generally the signal with the highest frequency» Typically drives a large load– all sequential logic elements– all precharged/dynamic logic– distributed throughout chip, so lots of wiring» DEC 21164’s clock accounts for 40% of total chip power– 3.75nF total clock load– 20W (out of 50W) in clock distribution networkLow Power Design for SoCs ASIC Tutorial SoC Clock.2 ©M.J. Irwin, PSU, 19991Processor Power BudgetsClockDatapathMemoryI/O (pads)Inner circle: low end embedded microprocessorNext circle: high end CPU with on-chip cacheNext circle: MPEG2 decoder ASICOuter circle: ATM switch ASICLow Power Design for SoCs ASIC Tutorial SoC Clock.3 ©M.J. Irwin, PSU, 1999Clock Power Reduction2P = CV fclock ddl Minimize voltage (V) using half swing clocksl Minimize clock load (C)» clock gating» careful routing, distributed driversl Minimize clock frequency (f)» DET flipflops» localized PLL to multiply frequency of clockl GALS design approachLow Power Design for SoCs ASIC Tutorial SoC Clock.4 ©M.J. Irwin, PSU, 19992Reduced Swing ClockVdd N-device clockP-device clockGndRegular ClockVddP-device clockVtpVtn N-GndHalf Swing ClockLow Power Design for SoCs ASIC Tutorial SoC Clock.5 ©M.J. Irwin, PSU, 1999Half Swing Clocksl Advantages» as long as Vtn (Vtp) less (greater) ...

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Power Reduction Techniques in the SoC Clock Network
Low Power Design forSoCs
ASIC TutorialSoCClock.1
Clock Power
©M.J. Irwin, PSU, 1999
Why clock power is important/large »Generally the signal with the highest frequency »Typically drives a large load – all sequential logic elements – all precharged/dynamic logic – distributed throughout chip, so lots of wiring »DEC 21164’s clock accounts for 40% of total chip power – 3.75nF total clock load – 20W (out of 50W) in clock distribution network
Low Power Design forSoCs
ASIC TutorialSoCClock.2
©M.J. Irwin, PSU, 1999
1
Processor Power Budgets
Clock Datapath M e m o ry I/O (pads)
Inner circle: low end embedded microprocessor Next circle: high end CPU with onchip cache Next circle: MPEG2 decoder ASIC Outer circle: ATM switch ASIC
Low Power Design forSoCs
ASIC TutorialSoCClock.3
©M.J. Irwin, PSU, 1999
Clock Power Reduction
2 P = CV f clock dd Minimize voltage (V) using half swing clocks Minimize clock load (C) »clock gating »careful routing, distributed drivers Minimize clock frequency (f) »DET flipflops »localized PLL to multiply frequency of clock GALS design approach Low Power Design forSoCs ASIC TutorialSoCClock.4 ©M.J. Irwin, PSU, 1999
2
Reduced Swing Clock
Vdd
Gnd
Vdd Vtp Vtn Gnd
Low Power Design forSoCs
Regular Clock
Half Swing Clock
ASIC TutorialSoCClock.5
Ndevice clock
Pdevice clock
Pdevice clock
Ndevice clock
©M.J. Irwin, PSU, 1999
Half Swing Clocks Advantages »as long as Vtn (Vtp) less (greater) than 1/2Vdd onoff characteristics of nfet (pfet) unchanged Disadvantages »sequential element delay approx. doubled (propagation delay and setup/hold time) due to increased onresistance »halfswing clock generator done via charge sharing, so sleep modes problematic »not appropriate for very low voltage systems
Low Power Design forSoCs
ASIC TutorialSoCClock.6
©M.J. Irwin, PSU, 1999
3
Clock Gating
Most popular method for power reduction of clock signals and fu’s Functional »often idle functional units unit – e.g., floating point unitsclock »need circuit to generate enablesignalenable – increases complexity of control logic – timing critical to avoid clock glitches at AND gate output »additional gate delay on clock signal – masking AND gate can replace a buffer in the clock distribution tree
Low Power Design forSoCs
A
ASIC TutorialSoCClock.7
©M.J. Irwin, PSU, 1999
Glitch Free Clock Gating
B
0 1
REG
<
Clock
Low Power Design forSoCs
<
Clock
<
Clock
(1)
(2)
Gated Clock
Gated Clock
ASIC TutorialSoCClock.8
From <
Clock
Gated Clock (1)
Gated Clock (2)
©M.J. Irwin, PSU, 1999
4
Gated Clock FSM Architecture
AF
Clock
Low Power Design forSoCs
Clock
Reg
Comb Logic
AF  Activation Function, Which evaluates to logic 1 when clock needs to be stopped.
Gated Clock
ASIC TutorialSoCClock.9
©M.J. Irwin, PSU, 1999
Clock Tree Construction to Facilitate Gating
HTree Clock Network
Low Power Design forSoCs
ASIC TutorialSoCClock.10
Can insert clock gating at multiple levels in clock tree Can shut off entire subtree if all gating conditions are satisfied
Idle condition
Clock
Gated clock
©M.J. Irwin, PSU, 1999
5
Clock Driver Distribution Comparison
Dimension (cm) 0.25 0.5 0.75 1.0 1.25 1.5 1.75
SD (W) 0.052 0.206 0.464 0.825 1.29 1.85 2.53
DD (W) 0.051 0.101 0.152 0.202 0.253 0.303 0.354
SD = single driver, DD = distributed driver (Htree) 3.3V supply, 100MHz frequency, 1 micron feature size
Low Power Design forSoCs
ASIC TutorialSoCClock.11
©M.J. Irwin, PSU, 1999
Clock Tree Structure Affects Gating
Clock
x1
x2 A x1+x3 B
x2+x4 (a)
R1
R2
R3
R4
x1
A Clock
B
x2
x3
x4
(b)
R1
R3
R2
R4
Assuming x1, x2, x3, x4 are mutually exclusive
Low Power Design forSoCs
ASIC TutorialSoCClock.12
©M.J. Irwin, PSU, 1999
6
Multiple Frequency Clocks
f < f1 < f2 < f3
System clock
Keyis in the design of the local circuits used to generate the clock signal in each module
Low Power Design forSoCs
f
f1
PLL
PLL
f2
Bus Interface
I/O controller
ASIC TutorialSoCClock.13
Parallel serial interface
RISC Core
PLL
f3
©M.J. Irwin, PSU, 1999
Clock Frequency Multipliers
Circuit
1 PLL
2 PLL
3 DDL
Tech
0.8m
0.5m
1 Young, 1992 2 Alvarez, 1995 3 Gupta Low Power Design forSoCs
Input Freq 50MHz
50MHz
33MHz
Vdd
5V
3.3V
3.8V
ASIC TutorialSoCClock.14
Power Diss 16mW
10mW
49.4mW
Area
2 0.31mm
2 0.52mm
©M.J. Irwin, PSU, 1999
7
GALS Design Style
Reduce clock power consumption by using a Globally Asynchronous, Locally Synchronous (GALS) design style Overheads for »local clock generation – independent clock generators – low power global clock reference signal with local clock frequency multipliers »global asynchronous communication Skew tolerant
Low Power Design forSoCs
data
handshake protocol
ASIC TutorialSoCClock.15
GALS Architecture
Low Power Design forSoCs
f1
PLL
Bus Interface
PLL
f2
I/O controller
RISC Core
ASIC TutorialSoCClock.16
©M.J. Irwin, PSU, 1999
Parallel serial interface
PLL f3
©M.J. Irwin, PSU, 1999
8
Key References
Alvarez, A wide bandwidth low voltage PLL for PowerPC microprocessors,IEEE Journal of SSC, 30:383391, April 1995. Chen, A simple technique for global clock power reduction, PSU Internal Report, 1998. Chen, Clock power issues in systemonachip designs,Workshop onProc. of VLSI, pp. 4853, March 1999. Friedman, Clock distribution design in VLSI circuits: An Overview,Proc. of ISCAS, pp. 14751478, May 1994. Gupta, Features of differential delay line used on the embedded ultra low power Intel486® in developer.intel.com/design/intarch/papers/ddl486.htm Hemani, Lowering power consumption in clock by using GALS design style,Proc. of DAC, pp. 873878, 1999. Kojima, Halfswing clocking scheme for 75% power saving,IEEE Journal of SSC, 30(4):432435, April 1994. Tellez, Activity driven clock design for low power circuits,Proc. of ICCAD, pp. 62 65, Nov. 1995. Young, A PLL clock generator with 5 to 110MHz of lock range for microprocessors, IEEE Journal of SSC, pp. 15991607, Nov. 1992
Low Power Design forSoCs
ASIC TutorialSoCClock.17
©M.J. Irwin, PSU, 1999
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